San Jose, Calif. A 644 MHz single-data-rate (SDR) LVDS reference design has been released for SFI-4 and 10-Gb sixteen bit interface (XSBI) applications. Built around the Virtex II and Virtex II Pro FPGAs, this reference design allows designers to use an SFI 4 interface to link a Sonet framer with 622-Mbps optical modules. Additionally, the reference design supports both 622- and 644-Mbps data rates for direct SFI-4 and XSBI interfacing to external 10-Gb Sonet and Ethernet devices.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.