TAIPEI, Taiwan Toshiba Corp. is putting the finishing touches on a 333-MHz fast-cycle random-access memory (FCRAM) that will usher in the second generation of its low latency memory line. This latest offering brings a 66 percent increase in bandwidth and up to a 20 percent boost in access time over the company's previous-generation device.
Toshiba is looking to strengthen its position in specialized memory for networking gear, where it faces off against a partnership between Micron Technology Inc. and Infineon Technologies AG. The duo calls its first device a "reduced latency DRAM," and it currently peaks out at 200 MHz, with a row-cycle time (tRC) as fast as 25 nanoseconds.
Toshiba's device trumps that. Using a 0.13-micron process, this 333-MHz upgrade reduces tRC to 20 ns and uses a double-data-rate (DDR) scheme to boost data transfer to 666 megabits per second, plus an additional two bits for error detection or correction. Toshiba has also increased density, from 256 Mbits to 288 Mbits, configured 4-M x 4 banks x 18 bits.
In total, Toshiba will offer three clock speeds in this generation, with clock cycle times of 3.0 ns (333 MHz), 3.3 ns (300 MHz) and 4.0 ns (250 MHz) and tRC's of 20 ns, 22.5 ns and 25 ns, respectively. In contrast, Toshiba's first-generation, 154-MHz part had a tRC of 30ns. Toshiba will offer samples in October for $45 each, and will be ready for volume orders in the first quarter of 2003.
The second-generation FCRAM also features lower power consumption a 2.5-V power supply and a 1.8-V I/O interface by limiting the active banks within the array.
"The first generation of FCRAM was basically a superset of the DDR DRAM so we were trying to keep as much compatibility with DDR DRAM, using the same package and the same interface," said Paul Liu, a senior manager for Communications Memory Products at Toshiba. "Here, to pursue higher performance, we are going with a smaller package, the 1.8-V SSTL interface and the unidirectional data strobe."
Toshiba's latest FCRAM chip, the TC59LM818DMB, is housed in a 60-ball BGA package.
The market for low-latency DRAMs isn't expected to gain traction until late 2003, and as it ramps up it is only expected to capture 1 percent to 2 percent of total DRAM revenues.
Although Toshiba and Fujitsu Ltd. developed FCRAM a few years ago as an SRAM replacement in cell phones, it also meets the minimum fast access and density requirements of network processors. Since then, Infineon and Micron have fielded chips and Samsung Electronics Co. Ltd. has licensed the Fujitsu-Toshiba architecture. All are targeting gear for multigigabit applications.
As the competition increases, these companies are moving quickly to broaden their product lines. Infineon said its 250-MHz and 300-MHz chips should roll soon, and designers are working on next-generation products that will be produced in a 0.11-micron process and scale to 400 MHz as a baseline, with a 20-ns row cycle time. Sampling is to start in the first quarter of 2003. Micron will follow a similar schedule.