Silicon-on-insulator (SOI) will continue to find its place in high-performance applications and branch out into some of the networking and communications space. Scaling presents challenges for all technologies, but for SOI there is an additional burden of preserving a performance advantage relative to bulk silicon. This will necessitate thinner film SOI substrates (T, Si<50nm) for="" reduced="" capacitance,="" favorable="" coupling,="" and="" well-balanced="" floating-body="" effects.="">50nm)>
In addition, more widespread use may occur if SOI can break the cost barrier either by substantial wafer cost reduction or by enabling a much smaller die size than could be realized in bulk silicon technologies. The latter could result from a novel system-on-chip or memory module such as the capacitorless 1T DRAM recently announced by the Swiss Federal Institute of Technology.
Thin-film silicon-on-insulator (TFSOI) is a semiconductor wafer technology that provides improved circuit speed and power relative to its bulk silicon counterpart and can possibly enable novel devices or integration.
Today, two SOI manufacturing methods are used for producing the vast majority of wafers: separation by implantation of oxygen (SIMOX) and wafer bonding. Both methods have been modified for improved quality and cost, with wafer suppliers inventing, acquiring, or adopting the full range of options. SOI material cost is high relative to bulk silicon or epitaxial wafers and can increase the fully processed wafer cost in the range of 10-20 percent. In addition, for leading-edge CMOS, there is very little die shrink due to the SOI isolation because most design rules have become lithography-limited.
The cost issue is a sizable barrier for proliferation of SOI because many applications cannot command a sufficiently higher price for SOI's traditional advantages of higher speed or lower dynamic power. For this reason, SOI has mainly found use in high-speed applications, or in some cases RF applications, where the isolation properties enable a favorable cost/value scenario. SOI transistor performance is improved over an equivalent bulk device because of the buried insulating layer in the wafer. This layer reduces the amount of electrical charge that the transistor has to move during a switching operation, making it faster and allowing it to switch using less energy (lower power).
These properties can be exploited further in circuit design through the use of higher stacked gates that would be prohibitive in bulk designs. Unfortunately, the same insulating layer that improves speed and power also bounds the body region of the SOI transistor such that its potential depends on such factors as the capacitive coupling to the gate, source/drain, substrate, and any other sources of charge generation or recombination. The body voltage directly affects the threshold voltage of the transistor and its switching characteristics, which means circuit design needs to account for these floating-body effects.
Some companies such as Motorola use internally developed compact models to accurately predict the floating-body behavior and enable LSI circuit design, while other companies find public-domain models offer reasonable SOI predictive capability.
An SOI CMOS process is similar in many ways to the bulk process. Key differences are in the isolation module and transistor integration for high performance while managing floating-body effects. In some cases, there are unique SOI material-to-process interactions that can cause yield loss if not properly modified and optimized. We have adjusted for interactions in shallow-trench isolation, transistor implants, salicidation, contact formation, and even the back-end-of-line (BEOL).
Around 1996, SOI technology development was being done on Motorola's most advanced CMOS platform. Feasibility demonstrations were performed using a 603 eV PowerPC microprocessor and a 4-Mbit asynchronous SRAM in 0.35µm and 0.22µm generations, respectively. That work showed SOI yield could be equivalent to bulk at improved speed and power. Motorola now has production and/or development in 0.1µm 0.13 µm , 90 nm and 65 nm SOI technologies. The 0.18 µm SOI technology in mass production offers core N and PMOS floating-body transistors, body-tied N/P-FETs, implanted precision resistors, zero-Vt NFETs, lateral P+/N well diodes, and N+/N well thin-oxide decoupling capacitors.
In the more advanced technologies, we have added multiple Vts, additional precision passives, dual- or triple-gate oxide thicknesses, and up to nine levels of copper metal with low k dielectrics to expand to more system-on-chip applications. Transistor performance is generally 15-20 percent better than the equivalent bulk node. Our highest performance devices in the 90 nm technology boast sub-6 psecond/stage unloaded inverter delay with well-controlled transient effects.
We have successfully introduced multiple SOI technologies into manufacturing. Run rates are high, and can frequently exceed 1,000 wafers per week. Yields in all our production SOI technologies match or slightly exceed the equivalent bulk numbers. For the most part, yield limiters are similar to those of the bulk process. However, a small number of SOI-specific materials defects are still apparent. These are "large-area defects" usually caused by wafer-bonding voids and can show up as a circular cluster of failed bits in bit-mapped memories.
SOI offers the opportunity to combine a variety of n- and p- type MOSFETs with up to nine copper metal layers. Combined with low-k dielectrics, and added features such as multiple voltage thresholds and precision passive devices, the materials system can realize between 15 and 20 percent better performance than bulk silicon alone.
Source: Motorola Inc.
In late 2001, Motorola began shipping the MPC7455 SOI microprocessor. This product is a member of Motorola's fourth-generation (G4) PowerPC family, and is derived from the original MPC7450, which was implemented in bulk silicon. It is manufactured in our 0.18 µm SOI technology featuring 65-nm gate lengths and six levels of copper interconnect. Initial SOI silicon showed a 20 percent speedup over bulk. The MPC7455 processor core supports a seven-stage pipeline, 11 execution units, and a memory subsystem that includes a 256-kbyte on-chip L2 cache. There are also on-chip L3 tag/status arrays to support the construction of an external L3 cache. The MPC7455 design includes 33 million transistors.
With over 750,000 parts shipped to-date, it represents a significant milestone for SOI. This SOI microprocessor has been recognized as "Best High-Performance Embedded Processor Chip" for 2001 by Microprocessor Report. The design currently supports frequencies up to 1.25 GHz. Certainly there is a long list of novel devices enabled by an SOI substrate or where the final device structure has both a front and back oxide. Today's planar CMOS SOI is a good stepping stone for novel devices and 3-D integration because the infrastructure, built for modeling and designing with floating-body devices, is highly leveraged.