As we move into the 21st century, substrate manufacturers will acquire more responsibility in IC development with more complex, partially processed substrates tailored to specific applications. However, more visibility of the IC integration process will be needed to enable the wafer manufacturers to develop the suitable wafer solutions in a similar manner to the evolution seen among the equipment manufacturers in the 1990s.
Exotic materials are now making their way into the silicon IC-manufacturing clean rooms. Lead-containing perovskites are being used for the development of ferroelectric RAMs, while iron (Fe) and nickel (Ni) alloys are the core of magnetoresistive RAMs. High-k dielectrics are being used to increase the capacitance of DRAM capacitors while reducing the cell size, and rare-earth oxides are being evaluated as an alternative to SiO2 for advanced gate oxides to ensure MOSFET scalability. The list continues.
At the same time, 8-inch substrate technology has matured with the introduction of nearly perfect crystal (NPC) wafers. Two major innovations at the substrate level have occurred: The development of 300-mm silicon has met the economy of scale of the 0.18-micron IC technology node with a more aggressive introduction for technologies below 100 nanometers. And silicon-on-insulator (SOI) has emerged to meet the IC requirements of improved performance while reducing parasitic substrate capacitances and leakage currents.
SOI substrates constitute a paradigm shift for the silicon IC industry. The early days, when SOI was used as a niche substrate technology for military or space applications, are long over. While Simox, wafer bonding and grind back-the first SOI wafer-manufacturing technologies-have strongly improved during the past 10 years, the SOI boom arrived with the breakthrough made by Smart Cut technology.
Developed by researchers at Soitec, Smart Cut is a bonding and thin-layer transfer technique, from a donor wafer onto a handle substrate. The transferred layer thickness is predetermined by the cleavage zone created via ion implantation (hydrogen, helium, argon). After the layer transfer, the cleaved surface of the thin film is treated, polished and annealed to ensure a silicon film and surface quality comparable to silicon prime wafers. The technology has been used to develop up to 300-mm SOI substrates that meet the most stringent specifications of the IC industry.
As the IC industry moves toward the development of the future 65-nm technology node, more innovation is required at the substrate level. The industry will likely experience a similar shift as the one seen in the '90s with the development of process modules by the equipment manufacturers.
Strained silicon is today one of the latest substrate developments, used in the manufacturing of very high-performance devices. The manufacturing of these substrates require several silicon (Si) and silicon germanium (SiGe) epitaxial steps to be able to obtain the strained-silicon layer at the substrate surface. As a function of the level of the built-in, strained-in Si lattice, an enhancement of the electron and hole mobility of up to 50 percent can be achieved, which translates into improved MOSFET performance. And while strained-silicon bulk wafers are still far from meeting the specifications of state-of-the-art Si and SOI wafers, development continues at a high pace.
The utilization of these new types of substrates faces many issues. The interaction of IC device integration and strained-silicon substrates needs to be well understood. The formation of the N and P MOSFETs, source and drain contacts, and isolation, may generate local stress and crystal defects that can lead to the relaxation of the strain of the surface-strained silicon. And a further challenge to the strained-silicon technology is the cost of such substrates. Smart Cut supports the development of ultrathin strained silicon-on-insulator, which will be needed by the fully depleted MOSFET architecture of the 65-nm node, while reducing the overall cost of ownership of such high-end substrates.
The development of ultrathin strained silicon-on-insulator is currently under way at Soitec to meet the future substrate needs of the IC industry toward higher-performing devices while keeping the power consumption at low levels. The strong synergy between the ultrathin SOI (less than 500- angstrom Si thickness on oxide) and ultrathin strained Si is one of the factors behind the fast development of this new generation of 300-mm wafers. The potential wafer solutions offered by technology such as Smart Cut are already much greater than just SOI and strained silicon-on-insulator.
A current development is silicon-on-quartz, which offers a single-crystal silicon layer on a fused quartz substrate-a development that will be extendable to silicon-on-glass. Silicon-on-quartz will enable the industry to couple for the first time the silicon IC state-of-the-art know-how with transparent substrates. And, the know-how acquired through SOI development has opened another door: the engineering of the bonding energy to allow postprocessing debonding of the structure-containing layer.
The debonding technology of IC-processed silicon layers makes it possible to obtain silicon films 100 times thinner than the state-of-the-art wafer-thinning techniques. IC wafers are lapped down to a thickness of 100 to 150 microns. The smart-card industry requires wafer thinning down to 40 or 50 microns.
With debondable Smart Cut wafers, wafer-scale processed silicon films can be obtained.
The availability of this wafer technology will empower the IC industry with a wide range of new solutions mainly in packaging, flexible smart cards and 3-D systems-on-chip. In order to reduce self-heating effects in ICs, heat-conducting substrates will be necessary, leading to a new generation of SOI wafers with a buried thermal sink.