Customers have many expectations when purchasing cellular phones. Long talk time and long standby time are clearly two of the biggest. But while existing 2G mobiles can talk for hours and last for days in standby, the same can't be said of emerging 2.5G and 3G cellular products. In fact, early trials in the Japan sector show some 3G mobiles powering down after under an hour of usage.
But, designers should be conscious of the fact that the answer to this problem does not lie solely in the analog or solely in the digital portion of a mobile design. To meet the demanding power requirements of end users, designers must implement a total power management scheme when developing next-generation systems. Let's examine each of these elements in detail, looking at the power management problems designers will face and some potential solutions to these headaches.
Laying Out the Elements
Before jumping into specifics, let's take a general look at the key areas where power management is a must in a mobile. Figure 1 portrays the major power consuming blocks in a typical 2.5G mobile phone design.
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Figure 1: Block diagram of a typical cellular phone.
The transmit power amplifier provides one of the main power management stumbling blocks for design engineers. This power amp requires a high peak current roughly 1 A. Thus, this component consumes more energy from the handset battery than any other component. Under typical user scenarios, the power amp will consume roughly half of the total battery energy.
The RF transceiver is not as power hungry as the power amplifier but also causes power concerns for designers. On average, the transceiver consumes between 50 and 100 mA power during either the transmit or receive modes.
In addition to the power is consumes, the transceiver poses an additional challenge for designers. Noise received from other power supplies for other components in the mobile can dramatically impact the overall performance of the transceiver. Therefore, designers must isolate the transceiver's power supply in order to combat potential noise problems.
The analog baseband device, which includes the audio codec, radio codec, and power control functions, does not consume high power levels, but must provide clean power to meet handset performance requirements.
The digital baseband device normally consumes more power than any other semiconductor component except the transmit power amplifier. Power consumption of the digital baseband IC is complex to understand due to many tradeoffs associated with the high processor clock speeds needed and the associated characteristics of the required wafer process. In general, wafer processes that can achieve high clock speeds for applications processing also have relatively high off-state leakage. This leads to an active component of power due to logic switching and a leakage component that consumes power whether the processor is switching or not.
Now that we've laid out the main power hogs in a mobile, let's look at some techniques designers can to solve these problems. We'll start with the digital baseband section.
Logic Function Headaches
The requirement for power management has existed, for battery operated or low energy devices, across generations of digital signal processors (DSPs). The main focus has been active power reduction, which for CMOS technologies, is defined by the consumption induced by signal transitions and node capacitance charging in the design. Hence, efforts for reducing this dynamic component have concentrated on clock control since clocks are the main source of activity in synchronous systems.
Partitioning of the system clock network into individual clock domains with automatic and software-aware controls has been and will continue to be an effective way to control clocks. Today, new clock techniques are also being introduced in DSP systems, like dynamic voltage and frequency scaling (DVFS), to further reduce the active power.
DVFS allows the operating voltage of a block of circuitry to be scaled up when the system is faced with a heavy processing burden, allowing clock frequency and voltage to be increased momentarily. System power is reduced by normally operating the system's circuits in a lower voltage and frequency mode, but moving to a faster, higher power mode only to handle peak data processing demands. It must be noted, though, that the continuous reduction in main supply voltage levels with technology (5 V then 3.3 V and 1.8/1.5 V, going down to 1.2 V and below) is limiting the real impact of DVFS, in synchronous circuits, due to minimum and maximum operating voltages becoming very close.
New power control challenges are also emerging for achieving static power consumption in baseband architectures. In modern CMOS technologies, the static power consumption of transistors has significantly increased, especially when supporting high performance operation. This is mainly due to geometry reductions and transistor threshold voltage tradeoffs needed to achieve performance requirements. This static component, or leakage, is sensitive to supply voltage levels. Figure 2 shows the evolution of dynamic and static power components for microprocessors (using high performance transistors, at maximum voltage).
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Figure 2: Evolution of dynamic and static power components in microprocessor architectures.
New techniques, still in the advanced development phase, to reduce the effect of leakage employ standby (or "sleep") system power states. These power states can either maintain the state of all or part of the system or to lose it. In the case where state is maintained, operating voltage reduction can be used, but special biasing techniques, applied in functions like memories and registers are required. In the case where state is lost, systems must switch off modules in the DSP and make sure these modules stay immune to operation in the rest of the system by electrically isolating the modules.
The leakage component of power can also be used as an indicator of the limit in total number of transistors that should be built for a given function. Transistors are not free, from both a static and dynamic power standpoint. Thus, modules must be optimized to employ the least amount of transistors possible.
You Must be Global
The discussion above shows why it is now required to introduce, at the level of a full baseband chip, a global notion of power management that re-groups clock and supply power controls into a common, consistent model for hardware and software designers. Power management requires a set of components to be interconnected for efficient control.
When dealing with the hardware portion of a baseband, designers must first careful partition the system into clusters (a.k.a. domains) of functions that share the same type of power modes (e.g., devices that can support voltage and frequency scaling and that can be switched off when not used versus others that must always operate at high active power state and must maintain their state). Secondly, these domains must be connected, for seamless chip level power management assembly, by standard methods in order to control the power states. This is achieved by having, for each domain, a power wrapper that allows the hardware to solve the intricacies of power state control within the domain and to evolve by including more sophisticated circuit techniques, as they become available.
Third, some logic functions that are shared between the domains (like interconnects, interrupts and wake-up events, and on-chip clock and power sources) must be treated separately by monitoring the power states of related domains. Special care must be placed on handling and switching between interrupt and wake-up events, based on power state evolution, since this is fundamental for insuring proper wake up of system parts that were shutdown.
Power consumption in the baseband's software components is mainly linked by the RTOSes ability to capture and model the evolution of activity requirements on hardware functions that are needed for the execution of a task. The software power manager can be split in three main parts. The first consists of means to capture information about the task to run, such as what resources of the chip will be needed dynamically, and what performance level (100% being defined by the highest frequency at the highest voltage) is required to meet the execution deadlines. APIs are now being developed to support this requirement. Some of the required parameters are difficult to gather and a default behavior enhanced by automatic profiling of access requests to devices like peripherals (which generally go through OS calls) should be provided.
The second part consists of a power and clock domain scheduler that is associated with the task scheduler in order to wake-up or shutdown the domains, to define the voltage level and frequency needed and take appropriate system state saving measures, based on underlying hardware capabilities and the deadlines ahead. The power scheduler also monitors the profile of the resources usage and takes decisions in liaison with the task scheduler so that shutdown durations are maximized.
The third part is a static allocation of power states to unused domains, depending on the configuration of the OS. This allocation can, for instance, decide if a peripheral resource can be fully shutdown if the corresponding drivers are not installed.
Figure 3 shows an example of hardware partitioning and power management component interconnection as well as the structure of the software stack. Such a combined hardware/software infrastructure of distributed power management approach was evaluated on a baseband chip for a 3G terminal (on a 0.1-micron process) and showed reduction in leakage of around 10 times in active and around 1000x in standby modes compared to classical clock management approaches.
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Figure 3: Hardware partitioning/power management component interconnection in a mobile phone architecture.
Although the analog functions of a cellular handset are not among the largest power consumers, power in analog functions is still very important and a good deal of effort has gone into reducing it.
The integration of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) into the system baseband logic function has been one avenue for reducing power in mobiles. Although loss of the precision matching components and higher voltage levels found in special analog processes create special challenges, circuit designers have responded creatively by maximizing use of digital functions to control and calibrate fundamental analog blocks, like ADCs and DACs.
One such technique, dynamic element matching, makes use of a matrix of elements that are switched to alternate states, creating a statistical effect on circuit performance that allows analog functions to perform as if the individual elements had better matching. Another technique is to maximize use of digital filtering, where analog performance is relaxed by simply shifting more of the filtering burden into the digital domain.
The integration of ADCs and DACs also reduces power consumption by reducing the number of pins used in high-speed digital interfaces between ICs. Since a single analog port on the system baseband processor replaces a digital interface whenever an ADC or DAC is integrated, power consumed at the interface is reduced. System digital noise coupling is also minimized.
Dealing with RF, Power Control Issues
The RF section of a cellular handset includes both a transmit power amplifier and a small signal transceiver. Presently, there are trends to adopt advanced CMOS technology or fine pitch SiGe processes to reduce power consumption in the transceiver. Special silicon DMOS processes or GaAs technologies are employed for reducing consumption in the power amp.
With the evolution to 2.5G and 3G air interface technologies, newer modulation schemes are required that call for mobile phone power amps to deliver a higher degree of linearity. In the face of these more stringent linearity requirements, power amplifier efficiency normally suffers by roughly 10 to 20 percent. Again, designers are looking at new techniques to overcome these challenges. Pre-distortion is an example of such a technique where input signals are altered to account for the non-linearity of the power amplifier, allowing the power amp to operate at higher efficiency levels while producing high accuracy modulation.
Power amplifier efficiency is also severely degraded when the output power is below the peak level. Since the typical handset is only occasionally used near peak output power (only when the user is near maximum distance to a cell tower), some handset designs are now employing DC/DC converters to recover efficiency in backed-off output power conditions. In typical user scenarios, the efficiency loss at maximum output power due to the efficiency of the DC/DC converter is more than offset by the gains achieved in backed-off conditions.
In the area of power management functions, integration is also a very important trend. The very large number of power domains used in modern processor designs, dynamic voltage scaling, and the requirement for additional body bias controls all lead to a very complex power management scenario for the system processor. In addition, integrated analog functions require very clean power supplies that are better served with full integration of the power regulators that feed the analog functions.
As RF/baseband integration takes place, several companies have announced integrated Bluetooth radios and cellular radios may well follow, the requirement for very clean, on-chip, power supply regulation will be even more critical. Of course, integration of power supply regulators in a digital CMOS logic process is a very challenging undertaking. Special transistor designs are required to meet the high voltage requirements imposed by the battery voltage, in some cases an external pre-regulator has to be employed to relax the voltage seen by the on-chip devices.
As this article showed, aggressive power control is essential in a modern handset design. Despite these challenges, designers are stepping up with a host of new power management schemes to reduce overall consumption in mobile and, in turn, improving standby and talk times in the very near future.
But, designers will continually be challenged as the 2.5G/3G revolution continues. Integrated cameras, color displays, interactive gaming and more will continue to push mobile power consumption to the edge, forcing design engineers to continually develop and employ new power management schemes. Through it all, the key to success will lie in taking a total system power reduction approach during the mobile phone design process.
Author's Note: The authors would like to thank Dave Scott, Uming Ko, Travis Summerlin, and Franck Dahan for their help with this article..
About the Authors
Bill Krenik is the wireless advanced architecture manager at Texas Instruments. He received a Ph.D. in Electrical Engineering from the University of Texas at Dallas in 1993. Bill can be reached at email@example.com.
Jean-Pierre Giacalone is the lead architect of the TMS320C55x DSP cores. In this role, Jean-Pierre helps define power management capabilities for this family of DSPs. He obtained a degree in microelectronics from the ENSEEIHT school in Toulouse, France, in 1985 and can be reached at firstname.lastname@example.org.