SAN JOSE, Calif. Defying today's harsh gravity in chip design, Cisco Systems Inc. may design more application-specific ICs this year than last, analysts and other sources said. While network processor makers hammer at its doors, Cisco is developing new ASICs for high-end packet processing and traffic-management applications.
The chips will power a huge, fast core router code-named HFR that Cisco is developing for first customer delivery late next year. The system would be Cisco's first multichassis router, competing with terabit-class router designs from Avici Systems Inc. and Juniper Networks Inc.
The HFR will consist of potentially more than a dozen separate chassis, including one that acts as a switch fabric, all connected by fibre-optic links. Each chassis will support 40-Gbit/second internal connections to its line cards.
Cisco is working with IBM Corp. on at least two 130-nm ASICs for the HFR. The devices are separate from the Toaster network processors Cisco developed internally for its 1-Gbit 10000 series and 10-Gbit 12000 series core routers. Although the company has hit some speed bumps using the IBM process technology, the HFR project appears to be on track.
At the Chip-to-Chip Conference here this past week, Cisco engineer Moshe Voloshin sketched a proprietary parallel interconnect Cisco is developing to link the two chips. That interconnect is expected to be faster and use fewer pins than the HyperTransport interconnect Cisco uses on other systems.
In his presentation, Voloshin discussed the problem of variations of up to 7 percent in path delays across chips built in leading-edge process technologies. Previous processes exhibited variations of only about 1 percent, he said.
Such emerging thorny issues are driving up the costs of developing ASICs and causing most OEM engineers to reduce the number of ASICs they develop. Nevertheless, Cisco is taking steps to slow the growth of its ASIC spending.
"These days it's more like we are trying to leverage a single ASIC design across three or four products, rather than build an ASIC for each platform. A couple years ago it was all about rushing products to market; now it's more about being cost-effective," Voloshin said.
"For high-end systems, a rule of thumb is keeping the ASICs at 16 mm or less on a side. The yields go down, and the costs go up dramatically even if you just go to 18 mm on a side," he said.