The days of the single gigabit backplane are out the door. Today, state-of-the-art systems typically run data rates of 3.125 Gbit/s across 20 inches or more of backplane trace. Next-generation high-end applications are taking these backplane designs even further, moving in the 6.25 Gbit/s and beyond.
At data rates beyond the 1-Gbit/s level, designers must compensate for new problems in their backplane architectures. The signal integrity of these high-speed serial links is affected by reflections due to impedance mismatches along the signal path, signal attenuation from backplane materials, added noise due to crosstalk, and inter-symbol interference (ISI).
Fortunately, designers can combat these problems through the appropriate choice of a serializer/deserializer (serdes) device. Serdes with integrated termination resistors, programmable output swing, transmit pre-emphasis and receive equalization can reduce the effects of impedance mismatch, attenuation, and noise problems and, in turn, improve an overall backplane design.
In this article, we'll examine the signal integrity designers will face when developing multi-gigabit backplanes. Then we'll show how the proper serdes can ease these challenges in a backplane design. Let's start by looking at reflections.
Dealing with Reflections
In the past, devices that drove backplane traces usually had signal edge rates that were more than twice the period it took for the wave to propagate through the trace. In these cases, simpler lumped element models were valid. However, at higher speeds transmission line effects dominate.
Impedance mismatches between a device driving a transmission line, the line itself, and the far-end terminations can result in large reflections on the line and degrade performance. These effects will appear as overshoot, undershoot, ringing, or stairstep waveforms on the trace if the load or the driver are improperly matched, as shown in Figures 1a and b. For high performance designs, matching is required. The ideal transmission line matches the impedance of the driver and the impedance of the load equals the characteristic impedance of the trace. In the examples shown in Figures 1a and 1b, the maximum power of the driving device will be transferred to the load.
Figure 1a: Impedance mismatches that can occur on a printed circuit board.
Figure 1b: Signal impairments introduced by the impedance mismatches.
A terminating resistor can be added in a backplane design to reduce or eliminate unwanted reflections on a transmission line and assure the best quality signals. The resistor can be placed external to the device or integrated into the silicon circuit.
While external devices are effective, the best option in today's high-speed backplanes is to have the resistor integrated on the serdes device. By integrating the termination resistor into the serdes, the signal quality is improved as a result of terminating closer to the end of the transmission line than would be possible externally. In addition, an integrated termination resistor can have a lower parasitic capacitance and inductance than an external resistor. The integrated resistor also eliminates discontinuities caused by unterminated stubs in the high-speed signal path.
Crosstalk is another factor impacting signal quality in multi-gigabit backplanes. Crosstalk occurs when the coupling of signals on parallel transmission lines creates noise on the line. Crosstalk arises from coupling on the PCB, both in the line card and the backplane, inside the package and within the backplane connectors.
Crosstalk can be categorized as either near-end or far-end crosstalk (NEXT and FEXT), with NEXT being much larger in amplitude than FEXT. In either of these categories, the amount of crosstalk is dependent upon signal amplitudes, signal spectrum, and trace/cable length. At higher bandwidths, these factors dominate and increase the error rate of the transmission.
When building a backplane, designers can minimize the effects of NEXT and FEXT by choosing a serdes that offering an adjustable transmit amplitude. To reduce crosstalk, the serdes should be set to operate at the minimum transmitter amplitude necessary to achieve reliable bit-error-rate (BER) performance across the backplane.
Having the integrated termination resistors on-board the serdes also helps squelch NEXT. For example, when two adjacent drivers send a signal in the same direction, the NEXT signal generated will travel back towards the driver. A well-terminated driver will curb NEXT, preventing it from reflecting back down the line towards the receiver. To ensure a driver is well terminated, the termination resistors must be as close to the driver as possible. This is achieved by integrating the termination resistors into a serdes device.
High-speed signals transmitted across a backplane will experience signal attenuation due to the skin effect and dielectric losses. The skin effect describes the phenomena of high frequency current traveling in the outer "skin" of a conductor, increasing the resistance to the flow of current.
The skin effect is caused by the self-inductance of a conductor, which causes an increase in the inductive reactance at high frequencies and forces the electrons toward the surface of the conductor. Thus, the high frequency component of the signal is attenuated.
At low frequencies, from 1.25 to 2.5 Gbit/s, skin effect and dielectric losses are equal contributors to signal attenuation. However at frequencies greater than 2.5 Gbit/s, dielectric loses begin to dominate as shown in Figure 2.
Figure 2: Attenuation in a 48-in. FR4 PCB Channel (Source: Howard Johnson)
An open eye at the transmitter can be closed at the receiver after it has passed through a backplane due the combination of skin effect and dielectric losses , as shown in Figure 3.
Figure 3: Example of a Non pre-emphasized signal, (a) Non pre-emphasized output at the transmitter (b) Closed eye seen at the receiver after 30-in. of backplane trace.
Pre-emphasis is one technique that is used to combat eye closure due to high frequency attenuation. Pre-emphasis boosts the higher frequency components of the signal, counter-acting the high frequency attenuation of the backplane traces.
At the transmitter, the high-frequency components of a signal are accentuated, or emphasized, so that by the time the signal reaches the receiver, via a PCB channel, the high frequency portion will be attenuated to the desired level. A pre-emphasized signal at the output of a transmitter is displayed in Figure 4a. After the signal travels through the backplane and is attenuated, the receiver sees an eye that is shown in Figure 4b.
Figure 4: Example of pre-emphasized signal, (a) Pre-emphasized signal at the transmitter output (b) Open eye seen at the receiver after 30-in. of backplane trace.
In applications with short backplane traces or intra-board traces, selectable transmit pre-emphasis can be used to allow the pre-emphasis to be disabled. However, when driving longer backplane lengths, pre-emphasis can be enabled to ensure an open eye at the receiver and a low BER.
Pre-emphasis has become a mature technology and most of the existing 10-Gbit/s serdes chips employ it. While some argue that pre-emphasis alone is a sufficient solution, there is another set of problems, such as ISI, which pre-emphasis only partially resolves at higher speeds. To tackle ISI at high frequency, a serdes device must also incorporate receiver equalization (more on this below). Unfortunately, most transceivers only offer pre-emphasis as a means to combat the signal degrading effects associated with high-speed backplane designs.
ISI is the spreading and smearing of symbols such that the energy from one symbol degrades subsequent symbols causing the received signal to have a higher probability of being interpreted incorrectly. ISI can be caused by many different phenomena including: filtering effects from hardware, frequency selective fading, non-linearities and/or charging effects. Very few systems are immune to ISI, and any high-speed communication system designs must incorporate techniques for controlling the impact of ISI.
As mentioned earlier, pre-emphasis alone at the transmitter does not effectively address the problem of ISI. Pre-emphasis helps to reduce ISI by providing some high frequency boost, but it has little effect on the frequency spectrum beyond (data rate)/3.
At slower signal rates, pulse widths are long and can be sampled far from the signal boundaries to avoid the symbol overlap. At faster rates, ISI becomes a more severe problem. Approaching 10 Gbit/s, ISI is no longer apparent only at the signal boundary and it starts to affect the whole width of the bit.
Using equalization, serdes transceivers can be tuned to minimize the effects of ISI. The key benefit of receive equalization is that it improves receiver performance without increasing the peak transmitter power.
Equalization at the receiver can be designed using either analog or digital (DSP-based) methods. The digital or DSP-based solutions use analog-to-digital conversion and digital filtering for equalization. The analog approach uses linear filter circuits to equalize the attenuated signals. Devices with programmable analog receive equalization minimize the effects of ISI. The programmable equalization paired with selectable pre-emphasis allows designers to fine-tune the signal integrity performance to their unique backplane environment.
In multi-gigabit backplane designs, several factors can contribute to degraded signal integrity including reflections, crosstalk, attenuation and ISI. As the article above demonstrated, these issues can be mitigated by the proper choice a backplane serdes that integrates termination resistors, programmable output swing, selectable pre-emphasis, and programmable equalization.
About the Author
Rachelle Trent is the serdes product line manager in PMC-Sierra's Enterprise and Storage Division. She received a bachelor of science degree in physics from the University of Victoria and a master of applied science (microelectronics) degree from Simon Fraser University. Rachelle can be reached at firstname.lastname@example.org.