SAN JOSE, Calif. Altera Corp. today will announce its long-anticipated Stratix GX family, which wraps programmable logic, source-synchronous I/O and multiple channels of fast serial interfaces onto one device. Altera said it expects to receive first silicon for Stratix GX in five weeks and should start general sampling in the first quarter of 2003.
The GX series pits Altera against Xilinx Inc. (San Jose, Calif.) and Lattice Semiconductor Corp. (Hillsboro, Ore.), which already are shipping field-programmable gate arrays with the 3.125-Gbit/second serial baud rate that is considered mandatory for next-generation backplane designs. One is 10-Gigabit Ethernet, also known as Xaui, which provides a way to join several 3.125-Gbit/s serial channels together. Networking gear makers are also looking at these speeds to connect their line cards through dumbed-down versions of Sonet, which is normally associated with long-haul optical networks.
But getting raw serial bandwidth is just the start for FPGA vendors adding fast serial I/O capability to their architectures as they struggle for sockets in networking backplanes. To comply with the newer high-speed communications protocols, FPGA vendors are tuning their I/Os and finding ways to condition the signals at the input and output to keep them from degrading as they traverse an FR-4 backplane. Altera, for one, said its GX can send and receive serialized data over 40 inches at 3.125 Gbits/s and still meet the specs; Lattice claimed it can do it over a 26-inch separation at 3.7 Gbits/s.
FPGA makers are also working to ensure that their chips can act as a bridge between serialized I/O and source-synchronous interfaces, both of which are considered prerequisites for future backplane designs. Serial interfaces typically employ a clock-data recovery scheme in which the clock and data are intertwined; slower source-synchronous interfaces keep the clock and data separate but in a tightly coupled pair.
Where FPGA vendors differ most is deciding whether communications standards should be implemented as dedicated ASIC circuitry or left to the FPGA fabric soft intellectual property (IP). At one extreme is Altera, which has included lots of dedicated circuitry for such standards as serialized Sonet and source-synchronous SPI 4.2. Lattice is also partial to including dedicated circuitry, though so far to a lesser extent than Altera. Xilinx, meanwhile, is taking the opposite tack by implementing more standards as soft IP cores in the FPGA fabric.
Tim Colleran, Altera's vice president of marketing, said Altera has potential customers and concluded that there was more to gain by homing in on a few standards that were most likely to succeed and then building in the hardwired logic to support them. The company's GX devices, for example, come with dynamic phase-alignment circuitry, which resolves channel skew for source-synchronous I/O so that it complies with the SPI 4.2 interface standard. Using a soft core for that function would have left the device susceptible to variations on heat and voltage, Colleran said.
"Building some of this stuff out of general-purpose [FPGA] is risky," he said. "[Customers] would prefer something in pre-verified hard IP."
But Xilinx argues that this approach sacrifices the kind of design flexibility that has been a hallmark of FPGAs. By building soft IP cores for the FPGA, the company got a head start on the SPI 4.2 standard and then added dynamic phase alignment when it became a requirement. Thus, Xilinx said, it can support a wide breadth of standards, including newer ones such as PCI Express and RapidIO.
Xilinx's strategy has given it a jump on interoperability testing. It plans to release results soon of a plug test conducted at the University of New Hampshire.
"We've focused a big portion of our IP on serial connectivity," said Per Holmberg, senior marketing manager of IP solutions at Xilinx. But the company is in the minority on the issue of hard vs. soft IP.
Like Altera, Lattice is pushing for more hard, preverified IP. The company is fielding separate devices for Sonet and Xaui interfaces, each supported by built-in hardwired IP. "It's our belief that for these fairly standardized portions of the protocol it's more efficient to implement in hard logic," said Gordon Hands, strategic marketing manager at Lattice.
Indeed, Altera's Colleran noted that Lattice, which acquired a serializer/deserializer (serdes)-capable FPGA last year from Agere Systems, has penetrated more customer accounts than Xilinx in backplanes. "We've probably seen more [Lattice] Orca design wins than V2Pro," he said.
One trade-off to including more hard IP is that it forces FPGA vendors to cut back on FPGA capacity. Using 0.13-micron design rules, Altera will offer between 10,000 and 40,000 programmable logic elements, Altera said. Lattice, which builds its parts using an 0.16-micron process technology from Agere, maxes out at 10,000 LEs. Xilinx, which prefers to measure logic density in "slices," said its highest-density Virtex 2 Pro provides the equivalent of 125,000 LEs.
Despite their disagreements on how to implement communications standards, FPGA vendors are moving in lockstep in other areas. In some ways, Altera's GX family is a harbinger of what's to come in serdes-based FPGAs. Like Altera, Lattice plans to introduce a product in the next few quarters that will have built-in dynamic phase alignment to support SPI 4.2, said Shakeel Peera, senior marketing manager at Lattice.
Meanwhile, Xilinx, which has a soft IP core for SPI 4.2, said it expects to soon characterize its silicon to support a source-synchronous data rate of 1 Gbit/s, a speed Altera said it can reach with the GX. Today, Xilinx's Virtex 2 Pro has a source-synchronous data rate of 840 Mbits/s.
GX also uses a signal-equalization feature, which negates high-frequency losses when the signal reaches the receiver, in addition to the more common pre-emphasis capability used to sharpen the signal at the transmit end. Xilinx said it intends to build this capability into the next version of its serial transceiver device.
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