The transition from second-generation (2G) to third-generation (3G) wireless cellular systems requires multi-standard adaptability in a wireless receiver. An important answer to this request is the use of delta-sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for aggressive digital signal processing, and at the same time, add adaptability and programmability to the characteristics of a RF receiver.
This articles addresses the issues of how to design effective delta-sigma modulators for wireless receivers that need to support GSM, DECT, and wideband CDMA (W-CDMA) operation. A single-loop third-order modulator topology suitable for low power and high integration multi-standard receiver is described.1 The trade-offs in the modulator design are also presented and explained.
In Part 1 of this article, we'll compare today's typical receiver architectures to the delta-sigma modulator approach. We'll also provide a look at the different types of delta-sigma modulators available and the key elements that make up a modulator designs. In Part 2, we'll further the discussion by looking at circuit implementation issues as well as the key sub-elements that make up a delta-sigma converter design. We'll also provide some simulation results as well as future design work that needs to be conducted in this space.
Over the past few years, the tremendous growth in the mobile communications industry has dramatically increased the number of subscribers to 2G digital cellular systems (e.g., GSM, IS-95/54, and GPRS), which were created to address the need for increased system capacity over first-generation analog systems. At the same time, the enormous demand for voice, data, instant imaging and mobile video services has led to the evolution of the wireless infrastructure to support third-generation (3G) standards (e.g., EDGE, WCDMA, CDMA-2000, and UMTS) and services.
However, a complete transition from 2G to 3G in a short period of time is not yet feasible, considering the vast volume of existing 2G services and the time, infrastructure, and capital expense needed to achieve competent quality and popularity for a ubiquitous 3G wireless system. In order to take advantage of both 2G and 3G standards and services during this transition period, quite a few research efforts have been made to create wireless transceivers that can provide either multi-band or multi-standard performance capabilities. 2,3,4,5,6,7
Accommodating multiple wireless standards in one single transceiver intuitively means additional complexity in both the RF and the baseband parts, which results in low integration and high power consumption. On the other hand, it is well known that area and power dissipation of digital circuits reduce as the fabrication process shrinks. Furthermore, the continuously downscaling of CMOS technologies has allowed for more aggressive digital signal processing at a lower price.
To take advantage of this in the wireless transceiver design, efforts are needed to convert the incoming analog signals into digital as close as possible to the antenna, which implies that most of the RF/IF (intermediate-frequency) and the entire baseband signal processing will be done in the digital domain. In addition, digital filters can provide the adaptability needed for multi-standard RF transceivers. However, the transition from single-standard systems to multi-standard systems is not at all trivial. It requires a complete reconsideration of the RF front-end design. The tradeoffs among performance, complexity, and expense make the design of a successful multi-standard receiver very challenging.
One notable challenge lies in the design of low-power, high dynamic range analog-to-digital converters (ADCs), which digitize the small signal in the presence of strong blockers and interferers. Since the neighboring blockers have not been satisfactorily attenuated by filtering (i.e., the bulky high-Q SAW filters in conventional transceivers are replaced by low-cost low-Q analog anti-aliasing filters), the desired small signal is submerged by them and won't be detected unless the ADC has high input dynamic range.
Delta-sigma modulator is one of the best solutions for this data acquisition interface because the quantization noise is shaped out-of-band with a high-pass characteristic, and the decimation filtering can be combined with selective digital filtering and IF mixing in order to attenuate both the quantization noise and neighboring blockers. Moreover, by choosing different sampling rates (i.e., different oversampling ratios), the same delta-sigma modulator architecture can adapt to the different signal bandwidth, dynamic range, signal-to-noise-ratio (SNR), and intermodulation requirements imposed by multiple RF standards.4 Additionally, compared to the nyquist-rate data converters, oversampled delta-sigma data converters have demonstrated lower sensitivity to the analog component imperfections, thanks to a higher sampling rate and more complex digital signal processing.
The desire to design effective delta-sigma modulators for low-power and high-integration multi-standard RF receivers has motivated research institutions and RF design organizations to dig into this topic. We'll look more at the design issues associated with developing these modulators below and in Part 2.
Receiver Technologies Review
Before exploring the design elements needed to make a delta-sigma modulator, let's first look at the common receiver approaches used in today's mobile phone architectures.
1. The Super-Het
The conventional super-heterodyne receiver has been a widely used topology in wireless design since its invention in 1917. It can attain excellent selectivity and sensitivity performance by proper choice of IF frequency and filters. It is not prone to the DC offset and LO leakage problems because it employs the two-step down-conversion scheme. In addition, when a high IF is chosen, the requirements of the image-rejection (IR) filter can be relaxed. However, the super-heterodyne architecture uses external IR and IF filters, which bring about a big disadvantage when it comes to the adaptation to an integrated solution.2
2. ZIF Receivers
The zero-IF receiver (also known as direct-conversion receiver) has been the outcome of eliminating the external IR and IF filters from the heterodyne receiver for the purpose of improving integration. In this topology, the entire RF signal spectrum is directly down-converted to baseband.
The direct-conversion topology no longer suffers from severe image interferences, but a time-varying dc offset is introduced at the mixer output due to the self-mixing of the original and leaked LO signals. Moreover, because this topology employs one-step frequency transition, and the channel selection is done mainly by a digital lowpass filter, a high-frequency, low-noise frequency synthesizer is needed to provide variable LO frequencies for channel selection, which is not easy to implement with the on-chip low-Q components. Finally, the dynamic range requirement of the base-band ADC is non-trivial since its input has not experienced much selective filtering.
The Low-IF Approach
The concept of on-chip bandpass filtering has led to the low-IF, single-conversion receiver topology. In this topology, the IF is chosen at a low frequency (typically hundreds of kHz) instead of DC. Thus, it alleviates most of the DC offset and low-frequency noise (e.g., flicker noise) problems, which appear in ZIF receivers.
However, due to its one-step down-conversion characteristic, the low-IF topology still suffers from the same design constraints that occur in the ZIF topology: a high-frequency synthesizer providing variable LO frequencies and a high dynamic-range baseband ADC. Moreover, the ADC has to be of wide-bandwidth (0 to 2 MHz), because the desired signal is usually more than two channels away from dc. Finally, a high-Q band-pass filter is needed to suppress the strong blockers folded in close to the desired signal.
The Wideband Double-Conversion Receiver
The wideband IF double-conversion (WIFDC) receiver shown in Figure 1 employs a two-step down-conversion as in the conventional super-het topology. The major difference between WIFDC and super-heterodyne receivers is that the second LO frequency (instead of the first LO frequency as in the conventional super-heterodyne topology) is made programmable to select the desired channel band.
Figure 1: Diagram of a wideband IF double-conversion architecture.
Compared to the ZIF topology, WIFDC mitigates the DC offset errors due to the LO self-mixing. Compared to the low-IF topology, it avoids the RF frequency-synthesizer because only low-frequency (on the kHz level) variable LO's should be generated, and it also removes the need for a high-Q band-pass filter.5.
However, in essence WIFDC carries out baseband sampling and channel selections, which implies adjacent channel blockers will cause severe DC offsets. As a result, a high dynamic-range ADC and a good anti-alias filter (AAL) are still needed. Finally, as shown in Figure 1, the elimination of the band-pass filter is achieved by adding more mixers at the second down-conversion stage, which cause extra problems in terms of power and LO mismatching.
4. The Digital IF Receiver
With the emergence of more advanced CMOS processes in terms of size, speed, and power dissipation, the IF-to-baseband conversion and filtering can be pushed into the digital domain. This transition from analog to digital will add more flexibility and programmability to the characteristics of wireless receivers. The digitization of the IF stage has been implemented in super-heterodyne with a high IF (i.e., about 100-MHz) architectures.
As mentioned in the previous sections, delta-sigma modulator is in favor because of its inherent programmability, which is essential for the realization of a multi-standard RF receiver. Also, its ability of performing sampling and filtering operations simultaneously makes it extremely attractive for the same purpose.
Figure 2 shows a digital high-IF topology using low-pass modulators for IF sampling. The IF-to-baseband section is split into two paths, which leads to a clock rate that is half the effective sampling rate.
Figure 2: Diagram of a typical digital high IF architecture.
One important advantage is that a high-IF digitizing has relaxed the requirements of image rejections, since the IF frequency is at least 10 times higher than the desired signal bandwidth. Low-pass delta-sigma modulators are chosen over the bandpass modulator to perform IF sampling and digitizing for the sake of lower sampling rates and hence power saving. In addition, a pair of lowpass modulators can achieve a channel bandwidth of 4 MHz when the IF sampling scheme is employed.
IF Sampling by Delta-Sigma Modulators
Figure 3 illustrates the noise transfer functions (NTF) for GSM and wideband CDMA (W-CDMA) when IF sampling scheme is employed. Instead of using a single sixth-order bandpass delta-sigma modulator with a high center frequency, a pair of parallel third-order, lowpass modulators offset by π/2 phase shift are used to acquire the same magnitude response. Compared to bandpass modulators, lowpass modulators ease the circuit design by lowering the modulator order and by reducing the bandwidth requirement. Moreover, the stability of a third-order modulator is easier to control than that of a sixth-order one.
Figure 3: NTFs for GSM and W-CDMA.
The specifications of a delta-sigma modulator are derived based on noise, intermodulation, and blocking performance requirements of the multi-standard receiver. Table 1 summarizes the radio specifications of the multi-standard wireless receiver.8,9,10
Table 1: Radio Specifications of the Multi-Standard Receiver
Both interfering and blocking signal levels must be taken into accounts in order to derive the required dynamic range of the modulator. The bottom line is that the residual dynamic range has to be covered by the overall dynamic range of the modulator.
As for SNR, the modulator's noise floor should be constrained to at least 10 dB below the noise floor of the RF front-end chain (i.e., from RF filter's output to modulator's input), so that its contribution to the overall noise figure (NF) is considered trivial. The derivation of the required IP3 is not easy because a reasonable estimation is not possible until all of the following figures are measured: the front-end chain gain, the attenuation of the interferers and in-band blockers by the IF filter, and the intermodulation performance (IP3) of the mixers.
Let's now take a look at what it takes to build a delta-sigma modulator. We'll start by looking at a concept for noise shaping.
Quantization of a continuous amplitude produces quantization errors in the time-domain. The correlation between quantization errors from sample to sample is largely broken if the input changes randomly by amounts much greater than the spacing of discrete levels.
Statistically, the mean-square value of the quantization error can be used to represent the quantization noise level, whose spectral elements evenly fall into the entire sampling bandwidth according to the additive white-noise assumption. Increasing the sampling rate to a level much higher than the Nyquist-rate can spread the noise power to a wide frequency range. The actual reduction of in-band power level is estimated by a factor of the oversampling ratio (OSR).11
In addition to the increased oversampling ratio (OSR), the delta-sigma modulator takes advantage of negative feedback to reduce in-band quantization noise power. Most of the quantization noise power would be pushed to higher frequencies. Figure 4 illustrates the process of first-order noise shaping as an example.
Figure 4: Diagram showing first-order noise-shaping.
Delta-sigma modulators can be roughly categorized into the following types: low-order single-bit single-loop, high-order single-bit single-loop, single-bit multiloop (cascaded or MASH), and multi-bit (single-loop or multiloop). Each topology has its own share of advantages and disadvantages. For example, a second-order single-bit single-loop modulator is robustly stable and easy to design, but it requires high oversampling ratio (e.g., 256 or more) in order to achieve a SNR of above 100 dB.
Table 2 compares the advantages and disadvantages of these modulator types.
Table 2: Comparisons of Modulator Types
Power and area are the two biggest concerns in regard to a multi-standard receiver, which must be taken into account in the design of delta-sigma modulators. The SNR vs. OSR ratio shown in Table 2 defines the modulator's ability of achieving high SNR for modest OSR values, which also indicates its adaptability to low power design.
Modulators with multi-bit quantizers are subject to DC non-linearity problems due to imperfect matching of multi-bit D/A levels, which lead to the need for auto-calibration or dynamic element matching techniques. The use of multi-bit quantizers and DAC error correction increases the complexity of the circuitry and hence more chip area and power budget.
Multi-loop or cascaded modulators provide guaranteed stability performance by employing lower order coders in each stage. However, the complete cancellation of the quantization noise from the first loop is not achievable unless a perfect matching between analog interstage gain and its digital prediction. Finally, both multi-bit and cascaded topologies impose additional pressure on the decimation filter since it must allow for multi-bit streams at it input, which increases the complexity of circuit design.
Thus, a high-order single-bit single-loop delta-sigma modulator is in favor because of its advantages shown in Table 2. However, a high-order single-bit single-loop modulator doesn't unconditionally guarantee stability. In fact, the STF and NTF responses should be analyzed carefully to ensure that certain stability criteria be satisfied .12
Fortunately, a third-order, instead of a fifth or sixth-order single-bit modulator, is needed in this tutorial in light of the selected digital high-IF receiver architecture and IF sampling. The effort to maintain stability is therefore greatly eased.
Loop Filter Design
Figure 5 shows a third-order loop filter proposed for GSM applications. The IF frequency is chosen as 78 MHz, and the ovesampling ratio (OSR) is equal to 192.
Figure 5: Loop-filter for GSM applications.
A third-order topology with a local resonator feedback (i.e., with optimized NTF zeros) is needed for W-CDMA since the signal bandwidth requirement has been increased to 1.92 MHz. Based on the modulator for GSM described in the previous figure, a slightly modified topology is derived for W-CDMA by merely changing the feedback factor from 0 to 1/9 (Figure 6). This means an additional local resonator feedback path will be activated for W-CDMA but disactived for GSM. In the real world, this can be realized by an AND gate in the driving circuitry of the NMOS switch. The IF frequency is now at 138.24 MHz while the OSR is equal to 24.
Figure 6: Loop-filter for WCDMA applications.
DECT and GSM will share the same modulator topology and system coefficients, as shown in Figure 5, except that the OSR value is now changed from 192 to 64. Since DECT's modulator uses the same topology as that for GSM, its NTF response and integrator output levels are somewhat similar to those acquired in the design of GSM's modulator. Alternatively, DECT can share the same modulator topology with W-CDMA but its SNR performance will get worse.1. For DECT applications, the IF frequency is now at 110.59 MHz, and the OSR is equal to 64.
On to Part 2
That wraps up Part 1 in our series on delta-sigma converter design. In Part 2, we'll explore circuit implementation issues as well as the elements that make a delta-sigma modulator operate. We'll also provide simulation results for the proposed modulator. To view Part 2, click here.
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About the Author
Mingliang Liu is a program manager at Foxlink International, Inc. Prior to this position, he served as a product development manager at Extron Electronics, and a product manager at AV Link. He holds a B.S.E.E. degree from Beijing Institute of Technology and a M.S.E.E. degree from Oregon State University.
Mingliang can be reached at firstname.lastname@example.org.