SAN FRANCISCO Fujitsu Microelectronics America Inc. officially unveiled a 10-Gbit Ethernet switch IC at electronicaUSA Tuesday (March 30). The company made special efforts to keep volume costs of the MB87Q3070 under $1000 a chip, by keeping protocol support to Layer 2 only.
Asif Hazarika, product marketing manager for the device and author of the Communication Design Conference paper, said that the "excess baggage" of Layer 3 protocols may be important for metropolitan applications, but not for the enterprise server clusters and data centers where the switch will be designed into.
The chip employs a unique interface macro, extended XAUI, which can be used in a standard fiber XAUI interface, or with the copper-based CX-4 standard in which four copper interconnects are multiplexed to meet a 10-Gbit channel speed at distances of up to 25 meters.
Hazarika said copper implementations in enterprise applications pit a CX-4 switch directly against Infiniband and similar protocols.
The 12-port switch is an augmentation of an earlier design Fujitsu offered for all-fiber 10-Gbit networks. The core clock speed of the chip is 312.5 MHz, and its aggregate bandwidth is 240 Gbits/s. The 728-lead BGA device is priced initiallyat $825 each in quantities of 10,000, with further price cuts anticipated.
The 10-Gbit switch is a natural adjunct to the "GigaPlatform" for the AccelArray structured array for communication and storage markets. The ASIC offers pre-diffused serdes macros, and other blocks to support up to 24 channels of Ethernet, ATM, and IP communication.
Currently, interfaces at 10 Gbits/s support only standard XAUI, though ASIC marketing manager Simone Shaghafi said "extended XAUI from the 10-Gbit switch is definitely in our roadmap for the AccelArray."
Fujitsu also used eUSA to debut the next-generation series of Mobile Media Processors, with dedicated MPEG-4 and JPEG codec blocks. The MB86V00 and MB86V01 are intended for mobile phones with advanced 2D and 3D graphics requirements. Codecs can be adjusted in speed to achieve the proper balance between performance and power dissipation, with the device consuming as little as 13 mW when the MPEG-4 block is clocked at 13.5 MHz.
Dan Landeck, marketing manager for wireless devices, said that the chip includes an ARM9 processor, though it is dedicated to hard-wired management functions and is not programmable. Graphics operations use a special scene-adaptive-motion estimation algorithm to reduce execution volumes. The current devices use an MPEG-4 core nicknamed "Owen," and a 3D/3D graphics accelerator called "Coral."
Future devices in the family also will include "Millenia," a color-interpolation image processing engine that can handle CCD or CMOS camera imaging up to 16 megapixels.
The chips, which include the 86V00 with 64 Mbits of SDRAM and the 86V01 without SDRAM, will be priced starting at $45 each in high volumes. They will ship with firmware that includes core object image-processing modules, source-code device drivers and source-code interface drive.