Irvine, CA--May 23, 1996--A second-generation 64 Mbitdynamic random access memory chip has been announced by ToshibaAmerica Electronic Components (Irvine, CA). There are several versions, in arange of multibit configurations: 16M by 4 bits, 8M by 8bits and 4M by 16 bits. All are fabricated in 0.35-micron CMOS,and each chip has an area of 167 square millimeters. They offerhigh speed and low power dissipation, and use Extended Data Out(EDO), to achieve an access time of 40 ns, while drawing100 mA current at 3.3 volts. A synchronous DRAM derivative is inthe final stages of development and is expected to be availablein early 1997.
These advanced products are the result of a co-developmentproject with IBM and Siemens. The 64 Mbit DRAM utilizes basicallythe same trench memory cell design that is used in the jointlydeveloped 256 Mbit DRAM. Capabilities and technologies developed inthe 256 Mbit DRAM project were applied to the 64 Mbit DRAM,contributing to smooth and efficient development of compact,reliable chips.
Major technologies contributing to chip performance include shallow trench isolation, which narrows the gaps betweentransistors with an oxidized isolation wall; and chemicalmechanical polishing, which supports precise processing of thechip by polishing the chip surface before each patterningprocess.
Sample shipments will start early third quarter 1996, at a priceof $450. Mass production is scheduled to start early fourthquarter 1996, at Toshiba's Yokkaichi Works in Japan. The newdevices are available in 400 mil SOJ/TSOP packages -- 32 pins forthe x4 and x8 versions, and 50 pins package for the x16 version.
Toshiba America Electronic Components Inc.
9775 Toledo Way
Irvine, CA 92718
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