SUNNYVALE, CALIF. -- June 3, 1996 -- An option to an existinggraphic tool accelerates the analysis of alternative designs, asa means of determining the best way to achieve a goal in thedesign of complex integrated circuits. The existing tool isSpeedCHART, a graphical means of generating a program in ahardware description language to control fabrication of such ICs;the new option is called SpeedExplorer, which reduces the time toanalyze a tentative design from hours to minutes.
Both SpeedCHART and SpeedExplorer are products of Speed, Inc., ofSunnyvale. SpeedExplorer is scheduled to be demonstrated at theDesign Automation Conference, opening today in Las Vegas, Nevada,at the Las Vegas Convention Center.
SpeedExplorer allows designers to specify their designconstraints within SpeedCHART, and to generate constraint filesin various forms to achieve their design goals. For specifieddesign and timing goals in SpeedCHART, designers can nowdetermine corresponding size and delay estimates automatically. It allows designers to concentrate on the design instead of onthe mechanics of analysis, and still to obtain analyses ofalternative designs quickly enough to complete a design cycle ina usefully short time.
Georgia Marszalek, (415)345-7477
Speed Electronic, Inc.
710 Lakeway, Suite 290
Sunnyvale, Calif. 94086
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