Sunnyvale, CA--June 17, 1996--ASPEC Technology Inc. (Sunnyvale, CA) announced Winbond Electronics Corp. (Hsin Chu, Taiwan) has licensed ASPEC's Open Design Implementation Technology (DIT) including the densest gate array architecture available, as well as the EDA design kit and custom compilers, for Winbond's 0.5-micron process. Winbond will use ASPEC's Open DIT to produce PC chipsets, multimedia products, HP PA/RISC-based microcontrollers, as well as other products to be announced at a later date.
As a major supplier of SRAM products, Winbond is actively ramping its logic product offering. In Spring 1995, Winbond began researching prospective design implementation technology experts who could provide the solution for its 0.5-micron logic product design technology. They reviewed benchmarks and product offerings from ASPEC and two other major US competitors. The 9-month evaluation ended with ASPEC winning by virtue of its breadth and depth of product coverage.
ASPEC will start to deliver products to Winbond in Q2 of 1996.
DIT is the technology that links EDA software/hardware and silicon manufacturing processes. In the past, DIT has been developed as a proprietary technology by each integrated circuit (IC) manufacturer. Open DIT is a commercially available system that can be used by ASIC vendors, IC/ASSP manufacturers, and system houses to target diverse silicon process technologies using any EDA methodology. The competitive climate of the semiconductor business of the '90's has propelled the need for Open DIT.
ASPEC's Open DIT contains dense, high-performance, low-power gate array, embedded array, and standard cell product architectures, cell libraries and design kits for popular EDA software, and optimized access to any silicon process.
Director of Marketing
ASPEC Technology Inc.
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