Fort Collins, CO--June 5, 1996--ASIC design kits thatsupport the new Standard Parasitic Exchange Format (SPEF) havebeen announced by Symbios Logic Inc. (Fort Collins, CO). The kits provide ASICdesigners with a more accurate representation of parasiticeffects.
SPEF is a new format that is jointly defined by Open VerilogInternational and CFI. It is part of the OVI/CFI DelayCalculation System standard, and can describe best, typical andworst-case parasitics in one file. By incorporating the SPEFstandard into its design kits, Symbios Logic enables ASICcustomers to shorten their development cycles and improve theoverall quality of their ASICs.
Semiconductor interconnect parasitic variations are independentof process variables affecting transistors, so a fourth variable,interconnect, is added to the three conventional variables ofprocess, temperature and voltage which must be accounted forduring ASIC timing verification.
SPEF provides additional flexibility, such as the capability todescribe the parasitics for certain nets in a detailed network ofresistors, capacitors and inductors, while other nets aredescribed in a reduced equivalent circuit format.
Lea Schwartz or Tony Greene
Symbios Logic Inc.
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