San Jose, CA--August 19, 1996--S-MOS Systems is now offering its new SLA9000F family of gate arrays, also referred to as the Excalibur program.
This new family offers eight masterslices and up to 44,000 raw gates (50 percent unilization) and is intended for customers with low gate count designs.
The SLA9000F is also a low-cost gate array, offering 0.6 m design rules at 1.0 m prices. To firmly establish this new family, S-MOS will forego NRE charges for units of 25,000 or more.
The Excalibur's turnkey model offers yet another benefit to customers with scarce design resources. For $15,000, S-MOS will take the customer's netlist and test vectors and convert it into a gate array design. This is particularly suitable for FPGA conversions without incurring the costs (often as high as 5X).
Using the Excalibur series as an entry-level ASIC design methodology, customers can utilize S-MOS' Seiko Epson manufacturing affiliation for volume rampup.
All masterslices offer on-chip dual level-shifters for mixed voltage (5.0 and 3.3 V) power supply options. Typical gate delays are .43ns at 3.3 V.
The library is available in a wide variety of QFPs, with pin counts ranging from 44 to 256 pins.
Software support includes a wide variety of in-house and third-party design tools on PC and workstation platforms. These include Synopsis Synthesis, and Cadence Verilog and Frontline Simulation.
For entry level and/or low-cost customers, S-MOS offers a PC-based tool called Auklet. This schematic entry tool interfaces with Cadence Frontline and is provided to the customer at no cost for the first 90 days.
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