Santa Clara, CA--September 23, 1996--NEC Electronics Inc. (Santa Clara, CA) announced OpenCAD Version5.0, an enhanced version of the OpenCAD Design System that enables customers to create designs with over five million gates and operational speeds of 250 MHz.
The OpenCAD Design System is a unified front-to-back-end design environment that allows designers to mix and match tools from some of the industry's third-party vendors (such as Synopsys, Mentor Graphics, andViewlogic) with those from NEC's offerings of proprietary software tools. This integrated collection of tools performs design functions such as schematic capture, logic synthesis, floorplanning, logic and timing simulation, layout, design and circuit rule check, memory compilation, and clock tree synthesis. NEC released its first design environment, OpenCAD Version 3.0 in August 1993. In September 1994, NEC released OpenCAD Version 4 which added increased tools support for 0.35 m drawn devices.
With OpenCAD Version 5.0, NEC adds support forViewlogic's Motive static timing analysis tool. In traditional signoff methodology, an event-driven simulator is used to verify timing through a process that requires the use of huge test pattern sets. However, in static timing analysis, the timing verification process is streamlined.
With Version 5.0, NEC offers customers three signoff simulators using the VHDL Initiative Toward ASIC Libraries (VITAL) standard. VITAL compliance improves the efficiency of simulation library creation, allowing NEC to quicly support multiple customer simulation requirements. The VHDL System Simulator from Synopsys, QuickHDL from Mentor, and V-system from MTI are all supported in Open CAD Version 5.0.
NEC Electronics Inc.
P.O. Box 58062
Santa Clara, CA 95052
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