Geneva, Switzerland--September 16, 1996--Meta-Software Inc. (Campbell, CA) announced that its MASTER Toolbox cell characterization and model generation toolset now automatically characterizes and generates Verilog models for complex cells, such as counters, shift registers, and LSSD's from Spice netlists. The MASTER Toolbox, version 4.1, also adds automatic model generation for Avant!'s Star-R smart RC extraction and delay analysis system, and for the Synopsys Design Power low power synthesis tool.
MASTER Toolbox automatically acquires all the data such as functionality, timing, and violations from circuit descriptions to create simulation, synthesis, power, and timing models for logic design. Models are generated for design tools from Cadence, Mentor, Synopsys, Viewlogic, and others. MASTER Toolbox supports the VHDL and VITAL standards. In addition, MASTER Toolbox automatically verifies all the models against Spice descriptions.
MASTER Toolbox, version 4.1 adds automatic model generation for Synopsys' Design Power synthesis system. Model generation for Zycad hardware accelerators and Cadence's TLF (Timing Language Format) have also been added.
Additionally, Avant! and Meta-Software have jointly developed a modeler for the delay calculator within Avant!'s Star-R 2.0. This modeler will be available directly from Avant!.
MASTER Toolbox pricing starts at $80,000. Version 4.1 for HP, IBM, and Sun workstations ships this month. Pricing options are available for modelers including Zycad modeler, Cadence TLF, and Synopsys Design Power.
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Campbell, CA 95008
Fax: (408) 371-5638
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