Synopsys Donation Enhances Open Standards
Mountain View, CA--September 16, 1996--Synopsys Inc. (Mountain View, CA) announced that it has delivered documentation of the Verilog register-transfer-level (RTL) synthesizable language subset for IEEE standardization via the EDA Industry Council. The VHDL synthesizable subset documentation is nearing completion and will be released shortly. As sponsor of the EDA Industry Roadmap, the Industry Council includes representatives from end-user companies, industry analysts, CAD Framework Initiative, European CAD Standardization Initiative, Electronic Design Automation Companies, Electronics Industry Association of Japan, IEC, IEEE, Open Verilog International, SEMATECH, and VHDL International.
The standardization effort began as part of the implementation phase of the EDA Industry Standards Roadmap. The RTL subset was identified as one of the high-priority, technology transfer projects necessary to implement the Roadmap. One of the goals of this effort is to formalize a proven standard that will address the interoperability issues that designers and vendors regularly encounter among EDA tools. A formal RTL synthesizable language standard will be the first among several standards needed as the industry moves to design reuse and systems-on-a-chip design methodologies.
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