Santa Clara, CA--November 25, 1996--QuickLogic Corp. (Sunnyvale, CA) announced that it has established a manufacturing partnership with TSMC (Hsin-Chu, Taiwan). TSMC will work jointly with QuickLogic to install QuickLogic's proprietary amorphous silicon antifuse technology into TSMC's 0.5 m, three layer metal CMOS process and subsequent smaller geometries. By migrating devices from a 0.65 m to a 0.5 m process QuickLogic is reducing its die sizes by 44 percent, and when combined with the wafer size increase from six in. to eight in., they will create some cost competitive devices.
TSMC will immediately start processing wafers in support of the rapidly growing demand for QuickLogic's pASIC 2 family of FPGA products. QuickLogic's nine usable kgate pASIC 2 device, currently in production on a 0.65 m CMOS process, will be the first product to be brought up on the TSMC fab. The high-density members of QuickLogic's pASIC 2 FPGA family will closely follow the 9K into production. All other pASIC 2 devices, currently on 0.65 m process, will be re-hosted to the 0.5 m process as a cost reduction strategy.
1277 Orleans Dr.
Sunnyvale, CA 94089
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