Sunnyvale, CA--December 18, 1996--Actel Corp. (Sunnyvale, CA) announced that it will donate ten of its Designer Series 3.1 systems to the University of Fudan in Shanghai, China, for use in the University's Electrical Engineering curriculum.
The Designer Series system is a comprehensive EDA tool for the students to utilize in the ASIC and FPGA design courses offered at Fudan. Each system will include the following:
- Direct Time Package
- Auto Place & Route
- ACTGEN (MacroBuilder)
- ACTMAP (VHDL & Retargeting tool)
In addition, Actel will provide third party tools fromViewlogic
--Viewlogic PRO Capture andViewlogic
PRO Sim--for schematic capture and simulation, respectively.
The ten systems represent a donation of over $78,000 to Fudan University. All systems will be supplied to the University by the end of July.
Each Designer Series toolset comes equipped with the ACTmap FPGA Filter, which provides logic synthesis and optimization from PAL language inputs or VHDL description, and the ACTgen Macro Builder, a parameterized macro function generator, which easily creates counters, adders, and other structured blocks. The design kits also include macro libraries, simulation models, and netlist interface routines.
955 E. Arques Ave.
Sunnyvale, CA 94086
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