Santa Clara, CA--February 20, 1997--VHDL International's User Forum, co-located again this year with the International Verilog HDL Conference (IVC), is slated to run from March 31 through April 3 at the Santa Clara Convention Center (Santa Clara, CA).
The combined conference, known as IVC/VIUF, will be highlighted by a series of tutorials, paper and panel sessions, and exhibits on VHDL and Verilog hardware description languages.
The keynote speaker is Michael Splain, CTO of Sun Microelectronics, a division of Sun Microsystems Inc. (Mountain View, CA). Scheduled for April 1, from noon to 1:30 p.m., Splain will review "The EDA Carousel"--a look at the evolution of computer-aided design methodology, offer insights into the future, and highlight several areas where design problems are surfacing.
VHDL sessions will address language issues, object orientation and infrastructure, modeling techniques, system design, the quest for VHDL simulation speed, high-level synthesis, and modeling and the delivery of intellectual property. A half-day tutorial program will be held March 31, with a full day of tutorials on April 3.
Four jointly organized panels will address: "Hardware/Software Co-Verification"; "Synthesis Above RTL--How Will We Get There?"; EDA in the Windows/Intel World: Design Issues on the Intel/Microsoft Platform"; and "Designing with Virtual Components: Terminology and Tradeoffs."
A luncheon panel session on April 2 at noon, titled "Finance and Wall Street: Savvy Investor's Secrets," will bring together financial analysts, an industry analyst, venture capitalists, and an investor relations manager to discuss EDA and the stock market. Cadence CFO, Ray Bingham, will moderate.
Conference and tutorial registration varies from $250 to $565. Exhibits-only passes are free and available at the door.
5305 Spine Rd.
Boulder, CO 80301
Return to Headlines