San Jose, CA--April 28, 1997--VLSI Technology Inc. (San Jose, CA) released details of two new deep submicron process technologies. The 2.5V optimized VSC9 measures in with a 0.25 m drawn channel length (0.18 m Leff) and 0.85 m fully contacted metal pitch geometry. Its sister technology, the 1.8V optimized VSC10 process, features a 0.20 m drawn gate length (0.15 m Leff) and 0.85 m full contacted pitch. Both processes deliver the same 35 picosecond (ps) inverter stage delay at their respective voltages.
Both processes are compatible with 3.3V I/O voltages. In addition, VLSI will offer a low-power version of the VSC9 technology designed to reduce standby current by up to 98 percent to customers who require ultra-low standby current for battery-powered applications such as cell phones, palmtop computers, and wireless data products.
VLSI will offer a range of packaging solutions to support different applications using its VSC9 and VSC10 technologies. For low pin count applications such as portable communications products, chip-scale packages with solder ball pitches of 0.8 m and below will be introduced late in 1997. For high-performance, high-pincount (1,000 leadcounts and above) applications, flip-chip packages with either ceramic or organic substrates will be available early in 1998. Flip-chip packaging will accommodate die sizes designed to a minimum slot pitch of 45 m. The processes will also be supported by existing wirebond-based families accommodating 60 m pad pitches. For medium pincount (300-600 leadcounts) VLSI has been using HBGA packages.
VLSI has provided early engagement libraries for the new processes to selected customers to enable initial design work. Production for the new processes will begin during the fourth quarter of 1997 in the VLSI San Antonio fab. The company will be prototyping some customer designs using the new processes in its San Jose pilot line from mid-year 1997.
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