San Jose, CA--April 24, 1997--Silicon Valley Research (SVR; San Jose, CA) announced that it has completed integration and testing of a new high-speed automatic placement technology resulting in improved design quality and turnaround time for SVR's SC and SonIC families of products.
The new placement technology named TeraCell has been developed by CLK Computer Aided Design Inc. (Fremont, CA), a development stage company. SVR has licensed the TeraCell placement technology which is being offered as an option to existing SVR installations, and with new product sales starting this month.
Silicon Valley Research San Jose, CA (408) 361-0333 Fax: (408) 361-0330 http://www.svri.com
Blog Doing Math in FPGAs Tom Burke 6 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...