San Jose, CA--May 29, 1997--Toshiba America Electronic Components Inc. (TAEC; Irvine, CA) announced a new family of 0.25 m drawn system-level ASICs integrating more than ten million usable gates at 42 ps. The TC240 is based on a new Unified Cell Array Architecture that provides designers with the flexibility of combining gate array cells, standard cells and custom blocks on the same die to achieve performance, functionality, cost, and time-to-market design goals.
The TC240 is targeted at high-density applications including personal computers, networking, advanced graphics, and set-top boxes.
The TC240 employs shallow trench isolation and a five-layer, no overlap, stacked via metal process to achieve 35 kgates per square millimeter gate density, or more than ten million usable gates on a die. Propagation delay of a 2-input NAND gate is 42 ps. Up to four metal layers are used for interconnects, while the fifth layer provides a bonding pad array for high pin count flip-chip designs.
TC240 is compatible with Toshiba's dRAMASIC families. The TC230D and TC240D 1T dRAMASIC families, announced last month, integrate up to 128 Mbit embedded DRAM and over 400 usable kgates.
TC240 uses a 2.5V power supply for the core logic; power consumption of a low-power, 2-input NAND gate is as low as 0.06 mW/MHz. To maintain a simple interface with existing peripheral devices, the I/O power supply is 3.3V. For very low power requirements, the internal power supply can be lowered to 1.8V, cutting power consumption by almost half.
A variety of system cores, functional blocks, I/O cells, and memories are available. The system cores are consistent with the Virtual Socket Interface Alliance principles. These system elements include:
- RISC microprocessor cores and peripherals based on the MIPS RISC architecture.
- CISC microprocessor cores and peripherals.
- Memories including dRAMASIC cells.
- High-speed I/Os.
TC240, like all of Toshiba's ASIC products, is fully supported by standard commercial EDA tools.
Available packages include high pin count, high-performance flip-chip BGA; low-cost TBGA and TAB-FP packages; and CSPs for minimum assembly space. Toshiba is actively soliciting design-ins and making production commitments. Production is scheduled for second quarter, 1998. Customers should contact their nearest Toshiba sales office for pricing details. Pricing depends on product complexity and packaging.
Systems IC Division
1060 Rincon Circle
San Jose, CA 95131
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