San Jose, CA--May 28, 1997--Alpine Microsystems Inc. (Campbell, CA) announced a new "Complex IC Technology" that connects two or more chips using a series of silicon-based substrates embedded within a standard surface-mount IC package. The result is inter-chip speed and I/O bandwidth equal to single-chip solutions, but at lower costs and higher levels of integration. Any IC can be integrated into a "Complex IC" without changes to design, fabrication, or test methodologies. Complex ICs currently in development include highly-integrated graphic subsystems, in which 2-D and 3-D graphic processors are combined with high-performance embedded memory.
Complex ICs provide several benefits that enable new generations of high-speed PC graphic subsystems with integrated frame buffers, CPUs with integrated L2 cache, and "system-in-a-package" applications.
Several IC manufacturers, including ATI, Atmel, and Trident are currently completing prototype designs. The first products will combine graphic accelerators and frame buffer memory to create high-performance graphic subsystems. An alliance of major memory manufacturers such as Fujitsu Microelectronics, Samsung Semiconductor, and MoSys facilitates the die-level availability of advanced memory technologies for integration into Complex ICs. Final packaging and assembly support is provided by key partners such as Amkor-ANAM, ASE, and IPAC.
Alpine's high-speed interconnect technology functionally integrates multiple ICs into a single cohesive system or subsystem. Complex IC technology is a multi-step process that integrates two or more standard or custom IC die in a standard surface mount package. This interconnect process occurs after the standard fabrication of the individual ICs and before assembly in a standard IC package.
To start the Complex IC process, each die is flip-chip bonded onto a chip-sized MicroPallet silicon substrate. Signal connections are made through a MicroPallet solder bump pattern that mirrors the bond pad pattern of the die. Since solder bumping and flip-chip bonding are automated processes, there is no variability in costs as pin counts rise. This approach also eliminates the inductive delays and yield fall out inherent in wire bonding technology, boosting performance, and reliability.
In the next step, two or more MicroPallet-mounted ICs are combined on a Micro-Board silicon substrate to form a highly integrated subsystem. Solder bump technology connects the MicroPallet substrates to the MicroBoard substrate. Completed MicroBoard Complex ICs are then assembled in standard ball-grid array or quad flat pack packages.
The MicroPallet and MicroBoard substrates incorporate a silicon-based interconnect architecture that integrates high-speed system-level signal routing. Featuring a single mask programmable switch matrix, the Complex IC interconnect enables rapid turnaround and simple design iterations. This interconnection scheme is implemented as a 50-ohm characteristic impedance stripline architecture, in which signal layers are offset between power and ground planes. This architecture creates extremely fast interconnect that can provide GHz-level edge rates.
Each die is tested after mounting to an individual MicroPallet substrate and before MicroBoard assembly, to eliminate compounded yield loss and the cost associated with "known good die." Complex IC processing begins with standard probed die. Analagous to board level testing, MicroBoard testing need only verify inter-chip signal continuity.
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