Synopsys Introduces Powergate for High-Accuracy Cell-Level Power Simulation and Analysis
Mountain View, CA--May 27, 1997--Synopsys Inc. (Mountain View, CA) introduced PowerGate, a dynamic simulation tool that analyzes power dissipation of cell-based designs. PowerGate works with Synopsys PowerArc, a new cell library power characterization tool that provides PowerGate with the data necessary to perform accurate dynamic power simulation. PowerGate and PowerArc are built upon the design technologies and methods of the recently merged EPIC Design Technology Inc. and are targeted for high-performance ASIC and structured custom IC designs.
PowerGate's simulation engine enables designers of complex ICs to accurately address the performance issues of deep submicron and nanometer designs by taking into account glitches, multiple transitions, "unknown," and high-impedance states. PowerGate's advanced algorithms also consider cell logic state dependency, multiple loads, partial swings, and nonlinear dynamic ramp effects.
Accurate dynamic power simulation is achieved with the Stepped Waveform Algorithm (SWA) technology. This precise modeling of power dissipation behavior by PowerGate at the cell level provides a high degree of precision required for deep submicron and nanometer devices. Considerations such as state dependency and signal transition history have a significant and profound effect on power dissipation as device dimensions decrease. PowerGate accurately models these effects at the cell level, as well as nonlinear device phenomena that dominate the deep submicron realm.
PowerArc provides PowerGate with a complete set of data necessary to take full advantage of SWA technology and to achieve the highest level of accuracy. Based on proprietary Synchronous Matrix Solver (SMS) technology, PowerArc characterizes cell power dissipation automatically and efficiently.
Working in conjunction with PowerArc, PowerGate is able to analyze non-synthesizable cells as well as standard library cells. Structures such as memories and I/O pads can be included for a full-chip dynamic power analysis. Supporting Verilog through the Programming Language Interface (PLI), PowerGate models the power consumption behavior of digital circuits based on signal activity information, as well as cell power characterization data. PowerGate fits into existing design flows and is compatible with industry-standard high-level simulation tools. The tool features an intuitive user interface and provides comprehensive power analysis reports. These reports include monitoring of power dissipation in hierarchical blocks, capacitive switching current, short circuit current, and time-average and peak power reports in interactive or batch mode. For post-layout simulations, PowerGate accepts SPF data.
PowerGate and PowerArc are available on CD-ROM for SunOS, SOLARIS, HP, and IBM platforms. Pricing varies, depending on configuration. The starting price for PowerGate is $33,000. PowerArc is available separately starting at $85,000.
Mountain View, CA
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