Sunnyvale, Calif.--June 24, 1997--At the Design Automation Conference (DAC) in Anaheim, Calif., on June 9, 1997, Avant! Corp. (Sunnyvale, Calif.) announced the release of Hercules Version 1997.2, their hierarchical physical verification system that addresses the special challenges of very deep submicron (VDSM) integrated circuit design.
Hercules 1997.2 offers 4x performance improvements as compared to previous versions, as well as new capabilities targeted specifically at VDSM. Its Hierarchy Optimization Technology (HOT) automatically optimizes the layout hierarchy to improve runtime and reduce memory. This new technology produces results that are up to 50 to 100 times faster than Cadence's Dracula. Hercules provides production-proven verification technology capable of verifying hundreds of millions of devices.
Using proprietary algorithms HOT eliminates the need for any special commands to recognize hierarchically formed devices. It automatically recognizes and extracts devices built across any type of hierarchy.
Hercules 1997.2 DRC and LVS performance is production-proven on a 300+ million transistor FPGA, a 256-Mbit DRAM and a six million-gate gate array. The runtime on the 300+ million transistor FPGA was less than four hours on a 200-MHz UltraSparc system, demonstrating the power of Hercules' capacity and performance.
Hercules 1997.2 also offers significantly improved LVS ease of use with its automatic recognition of equivalence points between schematic and layout. Users do not have to enter matching points manually.
Hercules 1997.2 runs on Sun Sparc, BP-PA, and DEC Alpha Unix platforms and is available now.
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