San Jose--June 23, 1997--Altera Corp. (San Jose) announced the FLEX 6000 family of programmable logic devices, which offer die sizes and costs directly comparable with gate arrays. This is made possible by the FLEX 6000 OptiFLEX architecture, which combines advanced bond pad technology, interleaved logic array blocks (LABs), and an optimized I/O structure to produce a new level of programmable logic efficiency.
The FLEX 6000 family will offer 10,000 to 24,000 gates of logic and will be manufactured on a 0.5-m, triple-layer metal SRAM process, moving to 0.35-m triple-layer metal process later this year. Family members will include Altera's patented MultiVolt feature that enables the I/Os to support preceding, current, and future-generation interface voltage levels. Family members will be PCI compliant and will offer pin migration to provide design flexibility.
Because of aggressive die size reductions, the FLEX 6000 family will be priced similarly to comparable gate arrays. For example, it is expected that a 10,000-gate EPF6010 device in a 144-pin TQFP package will cost $6 in volume by mid-1998. When gate array non-recurring engineering (NRE) costs are amortized across the gate array unit cost, FLEX 6000 devices can cost less than comparable ASIC devices.
This pricing is made possible by the enhanced OptiFLEX architecture. Every feature in OptiFLEX is targeted at producing maximum performance and utilization in the smallest possible die area. Through a feature called LAB interleaving, any LAB can communicate directly with an adjacent LAB through local interconnect, optimizing global row, and column resource utilization within the FLEX device architecture. FastFLEX I/O provides a direct path from the logic element (LE) to the I/O pin for fast clock-to-output timing. The OptiFLEX architecture also leverages an advanced bond pad pitch of just 3.2 mils to achieve maximum die size reduction. This means a 16,000-gate FLEX 6000 die with 240 pins will be only six percent larger than a gate array die with the same pin count.
A 16-bit loadable counter runs at 135 MHz in a FLEX 6000 device--more than twice as fast as competing field programmable gate arrays that typically run at 60 MHz or slower.
The EPF6016 with 16,000 gates is available now and is offered in a variety of package options including a 144-pin TQFP, a 208/240-pin PQFP, and a 256-pin BGA. The 24,000-gate EPF6024A will be available in the fourth quarter of 1997. The rest of the FLEX 6000 family is expected to be available in the first half of 1998. All will be available in a variety of packages, including PQFP, TQFP, and BGA. During mid-1998 for quantities of 50,000, the 5-V, 0.5 m-based EPF6016 is projected to sell for $7.50; the 3.3-V, 0.35 m-based EPF6016A is expected to be selling for $7; and the 3.3-V EPF6024A is projected to sell for $10.
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