Santa Clara, Calif.--July 24, 1997--National Semiconductor Corp. (Santa Clara, Calif.) announced availability of a fully DVB-S (Digital Video Broadcasting) and DAVIC- (Digital Video Audio Council) compliant QPSK (Quadrature Phase Shift Key) demodulator with integrated FEC (Forward Error Correction).
The all-digital NDV6201 demodulator meets all specifications of the fast-growing DVB-S/DBS (Direct Broadcast Satellite), and LMDS-Grade A (Local Multipoint Distribution Service) markets.
Dataquest predicts annual production of DVB-compliant DBS set-top boxes will grow to exceed 17 million units by the year 2001. DVB is now gaining fast acceptance within North America.
To meet the demanding bit error rate requirements for the DVB standard, the NDV6201 has a high tolerance for noise, distortion, and other impairments from a worst-case satellite up/down-link, LNB (low-noise block), and tuner. Unique built-in registers compute signal/noise ratios (SNR), allowing OEMs to detect system malfunctions quickly and reliably. The registers can also be used for antenna positioning.
The demodulator offers several key advantages over currently available designs. The NDV6201 is designed to demodulate and decode signals at all DVB symbol (baud) rates from less than one Msymbol/sec to 45 Msymbols/sec with a single 65 MHz clock and dual A/Ds.
This configuration supports existing satellites and will also support future satellites with different bandwidth and power specifications.
The sampling techniques eliminate the need for analog PLLs for both timing and carrier phase recovery. All-digital on-chip timing and carrier recovery makes the National chip suitable for a range of baud rates without external tunable analog circuitry, and without the need for external carrier and phase VCXOs (voltage controlled crystals).
Since the NDV6201 can be used with inexpensive off-the-shelf tuners and A/D converters the OEM can further reduce the cost of the set-top box.
The NDV6201 demodulator also supports the DAVIC, Grade A standard for LMDS applications including channel bandwidth from 20-40 MHz, and symbol rate from 14.61-33.33 Mbaud. Grade A compatible LMDS set-top box can easily be designed by programming registers in the NDV6201.
The NDV6201 demodulator consists of two major blocks: QPSK and FEC. The QPSK block integrates BPSK and QPSK, timing and carrier recovery, and match filters.
The FEC block integrates convolution decoder with depuncturing support for all DVB rates (1/2, 2/3, 3/4, 5/6, and 7/8), automatic rate adaptation and sync, de-interleaving with on-chip memory, Reed-Solomon Forward Error Correction, energy dispersal, channel error monitoring, uncorrectable block output indicator, MPEG-II sync byte recognition, and M-bus serial bus interface.
The NDV6201 is available in a 68-pin PLCC, and is manufactured with high-performance, low-power CMOS process. Samples of the NDV6201 are available now to Alpha/Beta sites. General sampling will begin in the third quarter of 1997 with volume production in the fourth quarter. The device is priced at $13.75 in 10,000-unit quantities.
Santa Clara, CA
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