Palo Alto, Calif.--July 21, 1997--Systems Science Inc. (Palo Alto, Calif.) announced a new VERA 1/4u 1/4s6TM 1/4s0 1/4d Verification System release, which includes a powerful source-level debugger for the VERA-HVL 1/4u 1/4s6TM 1/4s0 1/4d (hardware verification language), and links to Quickturn's emulators.
The VERA 3.0 release has focused on ease-of-use capabilities so that engineers can use VERA most effectively to verify the correct operation of blocks, ASICs, and complete systems.
VERA-HVL is a hardware verification language designed expressly for functional validation rather than for hardware design. The main benefit of using VERA to verify Verilog designs is that one can create much more exhaustive and stressful test conditions with less engineering effort than if one used a pure Verilog environment. VERA can be used with Verilog-XL, NC-Verilog, VCS, Frontline, and Speedsim simulators, and with Quickturn emulators.
VERA's new source-level debugger allows users to observe and control the many concurrent operations that may be going on at once in testbenches that exercise designs thoroughly. It has a flexible graphical interface, which is based on industry-standard Tcl/Tk, which is also compatible with standard Verilog graphical debugging environments. Engineers can setup breakpoints, see the different parallel contexts, find out about the status of different threads of execution, etc., as they thoroughly validate the design.
VERA 3.0 is available now on Sun and HP platforms. Unit prices for floating licenses range from $7,500 to $27,500, depending on the options.
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