Palo Alto, Calif.--August 25, 1997--Denali Software's (Palo Alto, Calif.) Memory Modeler, EDA software that allows designers to create models for new memory components or existing cores, is now available on Windows 95 and Windows NT, the company announced.
Memory Modeler's class-based software architecture provides designers with the needed structure for tailoring models to key specifications of the memory. It provides a rich modeling environment, accurate models, powerful debug capabilities, and is integrated with VHDL and Verilog HDL simulators.
Memory Modeler's class-based technology is based on a flexible software architecture that allows designers to tailor models to critical memory specifications. With Memory Modeler, designers characterize features, timing, and manufacturing of memory parts using an interactive fill-in-the-form interface. Interactive debug and test bench support features accelerate debugging and regression testing. Its simulation and analysis extends the simulation environment. Class-based, object-oriented models include DRAM, SRAM, SGRAM, SSRAM, FLASH, PROM, and FIFO.
Denali Software supports simulators and their proprietary modeling interfaces, including Cadence's Leapfrog and Verilog XL; FrontLine Purespeed; Model Technology's V-System; SpeedSim; Synopsys VSS; andViewlogic's Fusion, Vantage Optium, and Chronologic VCS.
Windows 95 and NT pricing starts at $5,000. Memory Modeler is also available on SunOS, Solaris and HP-UX operating systems.
Palo Alto, CA
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