Berkeley Heights, N.J.--Aug. 18, 1997--Lucent Technologies Microelectronics Group is offering two new Customer Solution Cores (CSCs) for high-speed data communications and telecommunications functions in its ORCA FPGAs.
The cores are precoded, pretested, and preverified building blocks that let equipment manufacturers incorporate these functions in their specific designs, and thereby reduce the times spent developing ATM systems.
The new ATM physical layer core complies with the ATM cell-based communications protocol and features 155.52 Mbps ATM line operation. The UTOPIA core, which provides the UTOPIA interface specification, supports both UTOPIA Level I and II operation at up to 50 Mhz.
The ATM physical later core implements the complete ATM physical layer of the ATM user network interface specification V. 3.1. into an ORCA FPGA. It also integrates the UTOPIA core to provide the ATM Forum's UTOPIA Level I or II interface to the ATM layer.
The ATM physical layer core features cell header detection and correction, cell payload scrambling and descrambling, idle cell insertion and deletion, out-of-cell and loss-of-delineation, and user-programmable cell filtering. In addition, the UTOPIA portion of the ATM core includes parity generation and checking for Level I and II interfaces, as well as support for all multi-PHY modes in Level II, and 25-MHz or 33-MHz UTOPIA operation.
The UTOPIA core features Level I and II parity generation and checking, multi-PHY mode support, and 25-MHz, 33-MHz, or 50-MHz operation. Both cores feature FIFO control and monitoring, and can use either 128 by 9 internal ORCA FIFOs or external 9-bit IDT722x1-type FIFOs. The standalone UTOPIA core can also operate with 16-bit datapaths and thus can use 64 by 17 internal ORCA FIFOs or 18-bit IDT7221x1-type FIFOs. The ATM physical layer core can be implemented in an OR2C/2T15A with external FIFOs oran OR2C/2T26A with internal FIFOs, and the standalone UTOPIA core can be implemented in an ORC2C/2T08A with external or internal FIFOs.
Both cores are supported by industry-standard synthesis and simulation tools, as well as ORCA Foundry FPGA layout software. The design package for each core consists of VHDL source code, a VHDL test bench, scripts and data files for behavioral and gate-level simulation, synthesis, and FPGA layout. Detailed documentation, including reference guides and user guides, are also included.
Both cores are available now in quantity. The ATM Physical Layer CSC is priced at $30,000, and the standalone UTOPIA I/II CSC is priced at $7,000.
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