Embedded Systems Conference--San Jose--Sept. 30, 1997--WSI Inc. (Fremont, Calif.) introduced their IC family that integrates, on a single chip, programmable system supervisory functions, a 2,500 gate CPLD, high density EPROM, SRAM, and extra I/O. Designed to provide flexibility and reliability to microcontroller-based embedded systems, PSD7XX devices also include a programmable interface to MCUs from Intel, Motorola, Phillips, Seimens, and others. The supervisory functions on PSD7XX devices include programmable power-on reset voltage, programmable reset pulse width, watchdog timer, and power-failure detection. Detection of out-of-tolerance voltage will enable SRAM write protection and battery back-up to preserve system data. All the supervisory functions can be programmed in less than a minute via a configuration menu in WSI's PSDsoft design tool suite.
The PSD7XX has an out-of-tolerance voltage detector that can be programmed to either of two trip-points (4.75 or 4.50 V). The trip-point can also be derived from an external source (1.4 to 5.0 V). As soon as the voltage falls below the programmed trip-point, the PSD7XX automatically disables any internal and external SRAM, as well as its own I/O. It also shifts to standby operation and switches to an alternative power supply (capacitor or battery), if connected. When the voltage level returns to normal, the PSD7XX can restart where it left off with the same data in the SRAM. A debouncing filter guards against false resets that might result from noise.
The watchdog timer on the PSD7XX operates completely independently of the microcontroller to protect the system against any glitches or erroneous code execution. It can be programmed to count from 1 microsecond to several seconds, using an internal 2 kHz clock or an external clock. Formulas are provided with PSDSoft design tools to generate a tightly specified long or short count from either source.
Power-on reset is required to clear any inappropriate conditions or registers in individual system ICs, including the processor. Different system ICs require varying reset pulse widths, the longest of which must be accommodated during power-on reset. The PSD7XX reset pulse width can be programmed to any value between 8 milliseconds and 1 second, based on either the internal 2 kHz oscillator or an external clock signal. The power-on reset voltage level can also be programmed to either of two pre-defined levels or by using an external voltage reference.
The PSD7XX has the equivalent of 2,500 gates of WSI's Micro-Cell-based programmable logic. Micro-Cells are special microcontroller macrocells that provide a direct bus connection between the logic flip-flops and the microcontroller. Conventional programmable logic architectures require the microcontroller to be connected to the logic through the PLD array, typically requiring the equivalent of 1,200 gates of logic to establish the connection. The direct access provided by the PSD7XXs Micro-Cell architecture saves as many as 30 macrocells and 32 product terms and cuts several weeks from the design cycle.
The general purpose programmable logic on the PSD7XX can implement dual processor interfaces, serial channels, mail boxes, keypad scanners, timers, counters, interrupt controllers, and shift registers. Altogether the PSD7XX has 12 output Micro-Cells, 24 input Micro-Cells, a dedicated PLD for fast (18 ns) select of seven external devices, and 27 I/O ports. Both the output and input Micro-Cells have a direct connection to the MCU address/data bus that allows the MCU to directly load and read the Micro-Cells at the flip-flop level.
The PSD7XX's 24 input Micro-Cells have a muxed flip-flop that can be programmed as an address latch, general purpose input register, or latch. The external chip select PLD provides seven fast chip selects without wasting valuable logic resources on the output Micro-Cells.
Each of the 27 I/O ports has a bi-directional connection to the address/data bus, a direction register, and a mux that allows it to accept output from the flip-flop or the PLD array. A control register allows the I/O pin to be programmed on-the-fly as a standard MCU I/O port, a PLD I/O port, an open drain, a latched address output, an input Micro-Cell, or a non-multiplexed data port.
A Micro-Cell allocator allows Micro-Cell outputs to be routed to other I/O pins, so that the Micro-Cell logic can be used even if its regular pin is dedicated to another function, such as MCU I/O. This is a unique capability. The pins of competitive non-Micro-Cell PLDs are dedicated to specific macrocells and the macrocell is lost if the pin is used for something else.
The fact that the MCU can communicate directly with the PSD7XXs flip-flops makes it ideal for implementing shift-registers, reading, and latching data only when valid and other functions associated with message-passing or mailbox-type applications in dual-MCU systems or systems in which the MCU must communicate with the outside world. The result is extremely efficient silicon utilization, predictable timing, and shorter product development time.
The PSD7XX is available with EPROM densities of 32, 64 and 128 kbytes. Designs that include OS kernels, use high-level languages or have multiple features implemented in firmware, will easily fit into the generous program store on the PSD7XX.
Production quantities of the PSD7XX are available now and are priced as low as $6.67 (PSD711S1-15J) in quantities of 10,000. PSD7XX devices are available in 52-pin ceramic and plastic leaded chip carrier packages.
The PSDSoft design tool suite is available now, for $495. PSDSoft with the PSDSilos Verilog simulator is priced at $1,295. Designers may purchase PSDSilos separately for $995.
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