Sunnyvale, Calif.--Sept. 29, 1997--Aspec Technology (Sunnyvale) announced 0.25 m foundry partnership agreements with IBM and UMC.
According to the agreements, Aspec will develop comprehensive 0.25 m DIT with both foundries and anticipate availability in the fourth quarter of 1997.
Aspec's 0.25 m DIT will include the company's patented High Density (HD) families of gate array (HDA) and standard cell (SSC) libraries, I/Os, design kits, memory compilers, and the necessary design methodology and third party tool support.
Until 0.25 m DIT is available, Aspec customers can design products for the readily available 0.35 m process technology and can then retarget their designs to the newer 0.25 m process technology through Aspec's QuickPort software. QuickPort ports the IC design at the layout level to the target process, optimizing for the target process parameters. In less than one hour per 100,000 gates, QuickPort produces a new layout for the design team to verify timing, and quickly go to production.
DIT is the technology that links EDA software/hardware and silicon manufacturing processes. In the past, DIT has been developed as a proprietary technology by each IC manufacturer. Open DIT is a commercially available system that can be used by ASIC vendors, IC/ASSP manufacturers, and system houses to target diverse silicon process technologies using any EDA methodology.
Aspec's Open DIT contains dense, high-performance and low-power gate array, embedded array, and standard cell product architectures; cell libraries and design kits for EDA software; quick and optimized access to any silicon process; in an integrated, proven methodology.
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Sunnyvale, CA 94086
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