San Jose--Sept. 23, 1997--Cadence Design Systems Inc. (San Jose) announced that its Verilog-based verification solution has set an EDA-industry record of 25,000 installations worldwide, with nearly 100 new customers signing on in just the first half of 1997. The company noted that its NC-Verilog simulator is rapidly gaining market acceptance and is largely responsible for reaching this unprecedented milestone. NC-Verilog accounted for more than half of the new installations with 1,100 licenses now in production use at more than 160 companies.
NC-Verilog provides the advanced technology, accelerated simulation performance, and overall productivity needed to verify large, complex systems. NC-Verilog's production-proven verification flow combines Cadence's Verilog-XL event simulator, Leapfrog VHDL simulator, and the new Cobra cycle-based simulator to satisfy the requirements of networking applications.
NC-Verilog features that target the unique characteristics of systems in silicon include:
- Fast, incremental compilation that reduces overall simulation initialization time for large designs
- High-speed event simulation that accommodates localized simulation activity in specific areas of the design
- An architecture that supports mixed-language design enabling early access to models, such as those VHDL models developed by networking IP providers
- Integrated event and cycle simulation methodology that maximizes performance across different design modules
- Highly accurate timing and compiled SDF annotation that facilitates reliable and efficient gate level simulation
- Links to Cadence and third party tools for system-level architectural design (Cadence's Alta BONeS design system), networking analysis, emulation, and hardware/software co-verification
Support for the new PLI 2.0 (VPI) standard for more efficient interfacing of C programs
The worldwide growth of Cadence's verification customer base was primarily stimulated by the performance and reliability of NC-Verilog. The latest release of NC-Verilog, which shipped in July, leveraged Cadence's native-compiled code architecture to accelerate simulator performance by as much as five times over the first production release in Dec. 1996. This latest release also implemented a proprietary predictive event scheduling algorithm to reduce much of the processing traditionally performed in other simulators. This generates an additional 2X speed-up in execution runtime by automatically eliminating unnecessary blocks from the event queue without requiring changes to circuit functionality or methodology.
Cadence's integrated verification environment includes the Verilog-XL, Verilog-XL TURBO, NC-Verilog, and Leapfrog VHDL event simulators, as well as the recently announced Cobra cycle-based simulator. U.S. list prices start at $25,000.
Cadence Design Systems
San Jose, CA
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