San Jose--Sept. 22, 1997--Xilinx Inc. (San Jose) announced delivery of the next version of its Foundation Series software. Xilinx Foundation Series version 1.3 software combines easy-to-use VHDL design tools, advanced synthesis and optimization technologies, and push-button design flows. Version 1.3 software also includes Xilinx's new architecture-specific optimization capabilities to balance area and speed tradeoffs for optimum design results. These advanced capabilities deliver a 20 percent improvement in design clock rates with reductions in synthesis run-times of up to 50 percent compared to previous versions.
Version 1.3 represents the first release of the Foundation Series solutions to deliver the advantages of the next-generation Xilinx software technology. The design implementation technology features advanced place-and-route software delivering incremental design capabilities called SMARTguide. These Xilinx-exclusive capabilities leverage results from previous designs' passes to reduce runtimes and shorten design iterations to under 10 minutes. As engineers incrementally design complex circuits, the SMARTguide feature allows users to work in their preferred methodology. Version 1.3 SMARTguide enhancements include timing repeatability and improved synthesis-based incremental design results. Additionally, new structured placement algorithms, automatically optimizing the alignment of busses using tristate buffers, circuit packing algorithm enhancements, and algorithmic improvements in timing-driven place-and-route capabilities all increase design performance by 15 percent, and deliver higher device utilization.
Foundation Series 1.3 software delivers mixed HDL and schematic design environments featuring new design entry capabilities, such as the integrated HDL Editor and the Language Assistant features, which make VHDL design creation more efficient and enable designers to complete push-button VHDL design in minutes.
The HDL Editor feature provides edit and search capabilities with language-specific color coding of keywords, as well as integrated on-line syntax checking to scan VHDL code for errors. The Language Assistant feature speeds design entry by providing a lookup list of typical language constructs and commonly used synthesis modules like counters, accumulators, and adders. The language assistant also provides support of pre-implemented or user-defined VHDL templates allowing users to quickly specify new design functions and re-use previously defined functions in new design projects and across design teams. Additionally, version 1.3 software includes a new graphical state editor that enables fast, intuitive graphical entry of both simple and complex state machines, including automatic generation of VHDL code for immediate design synthesis after entry.
Foundation Series 1.3 software supports the complete Xilinx XC4000XL FPGA family available now and the XC9500 CPLD family. The XC4000XL FPGA family has devices ranging in density from 466 to 7,448 logic cells and is available for -3, -2, and -1 speed grades. The XC9500 CPLD family combines Flash technology with an advanced architecture optimized for pin-locking and in-system programming (ISP) capabilities and ranges in density from 36 to 288 macrocells.
Foundation Series 1.3 software is available for popular PC platforms and supports both the Windows 95 and Windows NT operating systems. Foundation Series software pricing starts at $495 on PCs, with special introductory pricing starting at $99.
San Jose, CA
Fax: (408) 559-7114
Return to Headlines