San Jose--Sept. 24, 1997--Cadence Design Systems Inc. (San Jose) announced that Cypress Semiconductor Corp. (San Jose) achieved a 100-times reduction in full-chip verification run time by using Cadence's Vampire IC physical verification software during the design of its newest 4-Mbit SRAM.
Vampire delivers the performance benefits of hierarchical physical verification without sacrificing the accuracy and simplicity of flat verification. Vampire's advanced technology is based on Auto-Adaptive Verification, which greatly simplifies rule set development, and automatically handles differences in schematic and layout hierarchies. To aid ease of use and customer migration from flat to hierarchical verification, existing rule sets created for Dracula can be quickly translated for Vampire.
Key features include Hierarchical Design Rule Checking (Vampire HDRC) for identifying violations across hierarchy; Hierarchical Layout versus Schematic (Vampire HLVS) for automated handling of mismatches in schematic and layout hierarchy; Hierarchical Full-Chip RC Extraction (Vampire RCX) for full-chip performance verification; and an interactive debugging tool and user interface (VampView) for detection and correction of errors while the verification run is still in progress--which includes built-in safety features to eliminate unintentional data loss.
Cadence Design Systems
San Jose, CA
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