Viewlogic Creates New FPGA Synthesis--Aurora
Marlboro, Mass.--Sept. 22, 1997--Viewlogic Systems Inc. (Marlboro) unveiled Aurora programmable device synthesis which combines advanced architectural synthesis with vendor-specific optimization algorithms. This provides the best possible synthesis results for each programmable technology.
The number of FPGA design architectures is increasing and many vendors now support multiple architectures. The size of the FPGA in terms of gate count and complexity is following a parallel track to ASIC design trends including increasing speed. High-end FPGAs are currently around 100,000 gates and are expected to reach 400,000 gates by the end of 1998 with speeds approaching 80 to 100 MHz. It is critical for the FPGA synthesis tool to be optimized for the specific architecture in order to achieve both the cost (area optimization) and performance (speed optimization) goals of the designer.
The distinction between FPGA design and ASIC design is decreasing as designers' make trade-offs between faster design times at lower speed and functionality for FPGAs versus longer design times with higher speed and greater complexity for ASICs. Designers need the flexibility to move easily between design flows that they are comfortable with.
With the integration of Aurora into Workview Office,Viewlogic's Windows-based EDA tool suite,Viewlogic offers customers the choice of a complete Verilog or VHDL design process for programmable devices. Aurora will be teamed withViewlogic's IntelliFlow design-flow manager and either Chronologic VCS Verilog simulator or SpeedWave VHDL simulator, to provide designers with a new all-in-one toolset for designing FPGAs and CPLDs in their language of choice. IntelliFlow provides complete FPGA/CPLD design solutions for schematic, ABEL, Verilog, VHDL, and mixed schematic/language flows. The ability of IntelliFlow and the verification tools in Workview Office to mix multiple styles of design entry is suited to the needs of the next generation of FPGAs, where cores modeled in one language can be verified with programmable logic designed in another.
Aurora includes automatic datapath resource inference and sharing, counter recognition, automatic detection and optimization of finite state machines, timing specification spreadsheets, and other advanced features required to meet the needs of the next generation of FPGAs. In addition, Aurora boasts a new parsing front end that supports industry standard Synopsys Verilog HDL and VHDL synthesis.
Aurora is available now on Windows NT and Windows 95. ViewSynthesis customers will receive Aurora for VHDL Synthesis as a part of their maintenance update. Programmable hardware vendors Actel, Lattice, Lucent, and Motorola will also be upgrading their ViewSynthesis customers to Aurora in their future releases. Prices start at $8,000 for a node-locked license of Aurora for Verilog or Aurora for VHDL, when purchased separately. Aurora for Verilog and VHDL can be purchased together for $12,000. Existing ViewSynthesis customers can purchase an Aurora for Verilog, add-on license for $4,000.
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