Mountain View, Calif.--Sept. 22, 1997--Synopsys Inc. (Mountain View) announced an advanced version of its EPIC-based extraction, reliability, power and timing solutions for designs of 250 nanometers and below. Among the extensive set of improvements are greater performance for full-chip RC extraction in Arcadia, full-chip hierarchical reliability analysis in RailMill, and the integration of EPIC's Synchronous Matrix Solver (SMS) technology with verification tools.
Arcadia, a full-chip, net-based, advanced RC extraction tool for deep submicron and nanometer IC designers, now works at twice the speed. In addition, with the advent of multiple processors/systems, users can get even higher performance from the distributed processing capability of Arcadia. Results from a recent benchmark on a one million transistor microprocessor chip with about half a million signal nets was completed in about 48 hours on a single Sun UltraSparc2. Using distributed processing across six CPUs, the extraction was completed in an overnight run. On this same chip, an extraction of about 5,000 critical nets was completed in less than two hours.
To address cross-talk and signal integrity in multi-million transistor circuits, Arcadia's cross coupling analysis and new 3D correction capabilities achieve results to within four percent of Raphael, which provides higher accuracy than the short-cuts available in the market. An annotated GDSII user interface for a cell-based design flow makes it easier to adopt Arcadia without any changes to the designers' current methodology. Built-in RC reduction is also available to decrease data volumes for faster simulation runs.
In the deep submicron and nanometer range, wire temperatures produce more heat, thus reducing an IC's reliability. With a new feature to measure the effects of joule heating, RailMill can now accurately predict the behavior of wire temperatures. This allows it to offer more thorough reliability analysis. In order to meet the endless demand for better accuracy, capacity, and performance, the next release of RailMill will provide an integrated solution with a link to the ACE engine and a quick mode for voltage drop analysis that runs up to 100 times faster.
EPIC's ACE engine option to the PowerMill and TimeMill tools enables mixed-signal and analog simulation capabilities by using Synchronous Matrix Solver technology. In Release 5.1, DelayMill, PathMill, and PowerArc have also been equipped with SMS to increase their accuracy, memory efficiency, performance, and versatility in delay calculation and circuit simulation. SMS technology enables all of these products to effectively handle cross coupling behavior and array structures, such as memory circuits in system-on-a-chip designs.
The EPIC 5.1 software release has begun shipping and is available on CD-ROM for SunOS, Solaris, HP, and IBM platforms. Pricing varies, depending on configuration and location.
Mountain View, CA
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