San Jose--Sept. 22, 1997--Pericom Semiconductor Corp. (San Jose) announced a new family of low-skew CMOS PLL clock drivers capable of generating frequencies of up to 100 MHz.
The PI6C5930 family extends Pericom's SiliconClock product line of PLL-based zero-delay clock generators and is pinout-compatible with the QS5930 design. The PI6C5930 accepts a less than perfect clock signal, cleans it up, and buffers it via six balanced drivers for distribution to multiple loads. It can also be configured as a frequency doubler to boost clock speed. Clock skew between any two output drivers is less than 250 ps.
PLL clock drivers, also called zero-delay buffers because of their almost negligible input-to-output propagation delay, are designed for high-performance digital systems such as Pentium and PowerPC motherboards, PCI systems, PC riser cards, and audio/video cards.
Sample and production quantities of the PI6C5930 family are available now with speed grade options of 50, 66, 75, and 100 MHz. All products are available in the small footprint QSOP-20 package prices start at $3.24 in 25,000-piece quantities. To order samples, please visit Pericom's Web site (www.pericom.com).
San Jose, CA
(408) 435-0800 ext. 321
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