Redmond, Wash.--Nov. 24, 1997--Applied Microsystems Corp. (Redmond)announced the CoreTAP coverification developmentplatform for pre-silicon debug, test, and integration of microprocessorcore-based ASICs. CoreTAP brings visibility and control back tohardware/software integration that developers lost to complex system-on-chip(SOC) technology.
CoreTAP reduces the error rate among embedded core-based ASIC designs.Typical error rates can add three to four months to design time and lead tocostly silicon respins. CoreTAP, a small, portable networked instrument, canprovide developers with real-time visibility 30-50 percent earlier in thedesign cycle by showing the interaction of intellectual property, physicalhardware, and embedded software on the microprocessor core.
CoreTAP is the latest hardware/software verification solution resultingfrom a joint development agreement with Viewlogic Systems Inc. Initially,CoreTAP will be available for the ARM 7 processor, with subsequentprocessor-specific CoreTAP toolsets available in 1998.
CoreTAP integrates simulation, evaluation, and instrumentation technologyinto one hardware platform, enabling the user to explore software interactionwith both real and virtual hardware in a self-contained developmentenvironment. The user has complete access to all the features on theevaluation side. The simulation features provide a connection to Viewlogic'sEaglei and hardware models described in VHDL or Verilog. Finally theinstrumentation features provide the connection technology for the most commondevelopment tools including in-circuit emulators, logic analyzers, and softwareverification tools, such as CodeTEST software verification tools fromApplied Microsystems.
The CoreTAP simulation feature set includes functional and cycle-accuratesimulation of both the processor and the bus. This enhances the user's degreeof confidence in pre-silicon test results by exceeding the accuracy providedby Instruction-Set Simulator (ISS) technology. Simulation support is alsoavailable for both real and virtual hardware and other bus masters that viefor control of a common bus. CoreTAP simulation also houses the networked,shared memory resource for both software execution and hardware simulation.
With its ability to synchronize real to virtual time, CoreTAP enables theRTOS kernels to be ported and tested prior to silicon, which is done withoutkernel modification. Synchronization modes operate at the clock edge, clockcycle, bus cycle, instruction cycle, function level and program level as wellas fully asynchronous operation.
CoreTAP's evaluation toolset includes 32 Mbytes of memory and 2 Mbytes of flashmemory. An LCD display interface is included for testing driver software andhardware common to system-on-a-chip applications. Also included in CoreTAP'sevaluation feature set are a serial channel that can act as an iRDA driver ordebug port, an Ethernet channel that provides for TCP/IP drivers and enables ahigh-speed link to the hardware simulation environment, and a PCMCIA interfaceto develop driver software.
The CoreTAP instrumentation feature set includes the standard headerconnections to the necessary address, data and control signals to support theCodeTEST universal pod. It also offers a JTAG-style debug connection tosupport in-circuit emulators and a header style connector for logic analyzers.Access to the processors is designed for use with traditional in-circuitemulators from Applied Microsystems or other vendors.
The CoreTAP coverification tool is available from Applied Microsystems onNovember 24, 1997, with a delivery time of eight weeks upon receipt of order. Systemprices start at U.S. $20,000. Eaglei is available from Applied Microsystemsand Viewlogic. Prices start at U.S. $40,000.
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