San Jose--Nov. 24, 1997--Xilinx Inc., (San Jose) announced architectural details of a new series of high-performance, high-density, system-level design FPGA devices.
Named the Virtex series, these devices will target the rapidly growing demand in today's systems for devices that are capable of integrating varied, high-speed functions.
The wireless communication, telecommunication, and computer market segments are being driven to provide smaller, lower power, and more reliable products with more features fueling the need for system-level devices such as Virtex devices.
The Virtex series combined with Xilinx software represents a new platform in system-level design achieved through close strategic partnerships with leading EDA partners. Working with EDA partners has secured the immediate delivery of Xilinx Alliance serieslibraries to start Virtex designs now.
Xilinx and its partners have co-developed a high-density solutionfor ASIC designers resulting in higher performance, faster compile times, and innovations that push state-of-the-art methodologies for FPGA design.
The Virtex devices offer the Xilinx SelectI/O interface to multiple voltage and drive standards. Virtex architecture, with 2.5V supply voltage, offers devices capable of direct interface beyond CMOS and TTL logic.
Virtex series will also support important low-voltage standards such as LVTTL, LVCMOS, GTL+, and SSTL3. The SelectI/O interface allows a single device to interface to multiple standards simultaneously, eliminating the challenges of multiple signal standards in system design.
The Virtex series uses a segmented routing optimized for interconnect delays as a function of the distance, or vector, from source to destination.
Virtex devices contain interconnects of varied lengths, resultingin delays that are fast, predictable, and insensitive to minor changes in placement. These advantages of segmented interconnect become increasingly important in high-density design. Synthesis tools will accurately model interconnect delays in Virtex series without placement information.
The first Virtex devices contain 250,000 system gates and 316 user I/O lines and are expected to be available for sampling in the second quarter of 1998. Virtex devices offering up to one million system gates are expected in the second half of 1998.
San Jose, CA
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