Scotts Valley, Calif.--Nov. 24, 1997--GEC Plessey Semiconductors (GPS; San Jose) announced the GSC200 family of standard cell ASICs. Designed using GPS' latest high-density CMOS process, GSC200 achieves the highest gate density and lowest power consumption available today for low-voltage applications.
The GSC200 is optimized for power-sensitive applications. A 2-input NAND gate with two loads operating at 2V consumes only 0.07mW/MHz; a D-type, also driving two loads and toggling at 2V, consumes 0.56mW/MHz. To reduce power consumption even further, the core and I/O cells can be operated independently at either 3V or 2V, with 5-V tolerant I/O cells also available. Engineers can take advantage of the split power supplies to design extremely power-efficient solutions by running the core at 2V, while the I/O is operating at 3V or 5V.
The new standard cell ASICs are targeted at high-volume consumer, computing, and communications markets, which are driven by end-user requirements for low-cost and power-effective solutions. To achieve these demands within an ever contracting time-to-market window, manufacturers are using Systems Level Integration (SLI) as a standard for ASIC development. As the demand for SLI increases, design reuse, as well as the availability of a library of proven logic, is becoming as important as the ASIC architecture itself. GSC200 enables effective SLI, with a proven design methodology and complex IP blocks including the ARM7TDMI and OakDSPCore programmable cores as part of the SystemBuilder library.
GSC200 is based on GPS' proven 0.35mm CMOS process to achieve a gate density of 19,000 gates/mm2. When combined with the company's optimized cell library, this high gate density reduces die size for low-voltage designs, to provide manufacturers with the lowest possible unit cost. The GSC200 is also available with a fourth layer of metalization to drive routing efficiency up to 95 percent.
The core cell library is optimized for synthesis, making GSC200 a perfect vehicle for exploiting the wide range of IP blocks in the company's SystemBuilder library. In addition to the basic logic gates, the library includes oscillators, PLLs, and the high-performance ARM7TDMI and OakDSPCore programmable cores. A complementary range of analog cells is also in development, with release planned for the first quarter of 1998.
GPS also offers low-power, high-density RAM and ROM as compact custom blocks. Their unique compiled SRAM architecture enables packing densities that many competitors can only match using a full custom approach. A 64 kbit RAM block occupies only 2.4 mm 2.GSC200 is supported by GPS' proven ASIC design methodology. Along with advanced delay modeling to account for differing pin-to-pin delays and complex edge speed/load/delay relationships, GPS offers comprehensive design kits for a range of industry-standard CAE systems. The design kits support full top-down design flow with gate-level sign-off simulation on Mentor and Cadence platforms. A VITAL compliant library is also available. GPS' worldwide network of design centers provide engineering and CAE support to ensure a smooth route through the design process, faster sign-off and reduced time to market.
GPS is also offering the recently announced ARM-based Embedded Processor and Embedded Microcontroller products on GSC200 technology.
GSC200 Design Kits are available now on CD-ROM through all GPS sales offices and design centers. Non-recurring engineering charges for the GSC200 Series of standard cell ASICs typically range from $95,000 to $150,000.
GEC Plessey Semiconductors
1735 Technology Dr., Suite 240
San Jose, CA 95110
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