International Test Conference
by Tets Maniwa
Washington, D.C.-- November 3,1997--The International Test Conference opened with an address from Jim Healy, president and CEO of Genus Corp. (San Jose, Calif.). Healy noted the perceptions and realities within the rest of the electronics industry towards test. In general, the semiconductor industry views test as a non-value added operation, because test adds costs and time to new product development.
To counter these perceptions, test (especially the ATE portions) need to need to increase productivity and functionality while decreasing costs. The costs of test equipment is dropping as a percentage of the total manufacturing cost, in spite of increasing pin counts and costs per pin. VLSI Research (San Jose, Calif.) showed ATE accounted for 13 percent of total manufacturing costs in 1992, and dropped to 10 percent in 1996. Their projections are for continuing decreases to about 8 percent by 2002.
One key to the equipment issue is innovative architectures, but this change in architectures requires access to the latest technologies in semiconductors. The problem is to design the next generation testers with the current or last generation chips, since the semiconductor vendors are not interested in servicing the low volumes of chips consumed in the ATE market.
One potential source of assistance is Sematech, where some of the latest technologies are developed. Sematech and the SIA, however, may be out of touch with reality, since their 1994 roadmap calls for tester prices dropping to $400 per pin by 2010, whereas industry projections are for a 500 MHz, 2000 pin tester is projected to cost as much as $50 million.
At the same time that the semiconductor industry is calling for lower cost test systems, the system on a chip technologies are increasing the complexity and costs of test, in equipment and production test times. The more highly integrated system-level chips will require a new test strategy to address the diverse embedded components and complex interactions within the chips. The system on a chip design will require cooperation between design and test early in the design cycle so the test engineers can ensure testability before the system architecture becomes fixed and more difficult to modify for test concerns. The test architecture must address the connectivity and functionality of all the internal components in minimal test time.
Some companies are starting to view test as a core competency that can help to differentiate the company and product development processes. The ability to develop on-chip test for complex integrated circuits can help to control the cost of on-chip test and permit the substitution of lower cost testers for production. The remaining problem is how to test the test circuitry in an on-chip environment.
Another issue affecting the perception of test is the serial nature of test development. Test development usually doesn't really start until the IC is available. Potential improvement in this situation is the introduction of virtual test development. This requires the ATE manufacturer or some third-party developer to develop and support software models for the testers, but reduces the need to tie up an expensive tester for hardware and software debug operations. The virtual tester allows better interaction between test and design by linking the test design environment with the design simulation environment.
The availability of virtual test accentuates the need for links of data from test and process. The manufacturing functions need better use models to permit the manufacturing software to take better control of the existing chaotic and non-linear use functions of test equipment. Current estimates are that test equipment is only in use 30 percent of the time. The manufacturers want to use their production scheduling tools to evaluate their flows, but this requires better interfaces and accurate tester through-put models.
The long term solution to improve the cost effectiveness of test is to develop innovative testers with links to design, process, and manufacturing data. This will enable the following changes in the design and test environment:
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- Enable better test strategies, because the test development will start earlier in the design cycle, and therefore will have more input into the design
- Enable more accurate tester models that will allow virtual tester development and also will link to manufacturing scheduling software
- Link process and test data to coordinate process enhancements and yield analysis
- Encourage the development of supply chain modeling software
- Start consortia to address the core problems in test and equipment
- Elevate the status of test from a secondary manufacturing function to a vital part of the design team