San Jose--Nov. 18, 1997--Cypress Semiconductor (San Jose) introduced its first SRAM built in a 0.35-m feature size.
The introduction comes on the heels of Cypress's first 0.5-mproducts in 1996, and represents a checkpoint in its efforts to scaledown its six-transistor cell technology to 0.25-m line widths orsmaller. The new 0.35-m device, the CY7C1021, is a high-speed, low-power SRAM aimed at phones, radios, modems, and other applications that employ digital signal processors (DSPs) or high-performance microcontrollers.
Cypress also announced that it has already achieved working silicon on products with 0.25-m line widths. The company expects to have production availability of quarter-micron products within the next six to nine months.
Cypress's six-transistor cell design is now used for all of the company's new SRAMs. Cypress's SRAMs have extremely low standby current. The six-transistor cell also eliminates susceptibility to alpha particles that can corrupt the value of data stored in memory.
The CY7C1021 is a 1 Mbit asynchronous device organized 64K by 16 in order to interface with 16-bit DSPs and microcontrollers. Its 0.35-m, six-transistor cell provides a unique combination of high performance and low power usage, with a 10-ns access time and standby power usage as low as 300 microamps. The CY7C1021 is offered in industry-standard 44-lead SOJ and TSOP II packages. It is also offered in Cypress's first chip-scale package, a 48-ball mini BGA that measures only 7.25 mm by 7.25 mm.
The CY7C1021 is offered in both 5- and 3.3-V versions. It is available in production volumes immediately in SOJ and TSOP II packages. Samples are now available for mini BGA packages, with production volumes in the first quarter of 1998. Pricing for the CY7C1021 starts at $5.45 in 10,000-unit quantities.
San Jose, CA
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