Palo Alto, Calif.-- Dec. 29, 1997--Hewlett-Packard Companyannounces a new series of benchtop logic analyzers with a built-inpattern generator that provides stimulus for functional testingof digital designs.
A logic analyzer with a built-in pattern generator allows designers to test system subcomponents earlier in the design cycle bysubstituting the pattern generator for incomplete boards, integrated circuits, or buses. This parallel development of subsystems allows problems to be detected earlier in the development process, without having to wait for the unfinished components. The substitution of the pattern generator for missing components also can help improve the quality of the finished product, because test and verification of the design can proceed when components are missing or late.
Prior to the HP 1660CP series, stimulus was available only in high-end modular logic analysis systems, such as the HP 16500C, and cost-conscious designers often spent time developing custom test hardware to provide stimulus. Although capital-equipment budget was saved, time-to-market opportunities often were sacrificed because time was spent developing custom test hardware rather than the end product.
The built-in pattern generator also allows software developers to create infrequently encountered test conditions and verify that theircode works before the hardware is available. Engineers can generate the patterns necessary to put their circuits in a desired state, operate them at full speed, or single-step them through a series of states.
The HP 1660CP series offers four models, with varying state and timing channels. Each model has 100-MHz state analysis and 250-MHz conventional timing analysis on all channels, with 4-K memory depth per channel. In half-channel mode, timing-analysis speed is increased to 500 MHz and memory depth to 8 K. The pattern generator provides 258,048-vector deep memory and up to 32 data channels at 100-MHz clock speed and 16 data channels at 200-MHz clock speed.
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