San Jose, Calif.--Dec. 22, 1997--Atmel Corp. has introduced a library of fully-defined, characterized IP cores for digital signal processing (DSP)functions for use with its AT6000 family of DSP coprocessor FPGAs.
Included with Atmel's FPGA designer software, the library currentlyincludes six fully-designed, fully-characterized "hard" IP cores of bit-serialdigital filters, including industry-standard 8-, 16-, 32-, 64-, 128-,256-tap finite input response (FIR) digital filters. These digital filtersare commonly used for signal conditioning, anti-aliasing, frequency bandselection, decimation, interpolation, and image convolution. Otherintellectual property cores of frequently used DSP functions are underdevelopment and will be added to Atmel's DSP IP library as they are completed.
Atmel's IP cores are fully reusable "hard" cores that designers can useas-is in any AT6000 FPGA. The cores can be optimized for performance, pitch,or area, or they can be used as the basis for more fully customized designs,using the DSP function generators in Atmel's FPGA Designer 5.0 EDA tool suite.
Atmel's AT6000 family of DSP coprocessor FPGAs are used to off-loadcompute-intensive datapath functions from DSP processors intelecommunications, networking, multimedia, data acquisition, and othersystems. AT6000 FPGAs can be dynamically reconfigured during system operationto accommodate changing constants, coefficients, or DSP algorithms. Atmel'spatented Cachelogic extends AT6000 silicon use by allowing portions ofthe device to be reused by functions that are not in use 100 percent of thetime. Atmel provides the world's only design tools to support dynamic, partial FPGA reconfiguration from a single FPGA design.
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