San Jose--Jan. 27, 1998--Compilogic (San Jose) has introduced C2Verilog, a unique EDA product that accelerates the high-level system design of complex FPGA and ASIC hardware. C2Verilog is the first in Compilogic's new series of C to HDL compiler products and will debut at the DesignCon 98 conference.
C2Verilog compiles ANSI C designs and algorithms into synthesizable RTL Verilog, which can be synthesized into FPGA and ASIC hardware. It supports the complete ANSI C language, including pointers, loops, and functions, without requiring special commands or C language restrictions. The C2Verilog compiler operates on both Unix (SunOS, Solaris, and HP-UX) and Windows (95 and NT) systems.
Now systems engineers proficient in C language design can create hardware without having extensive HDL experience. Engineers can take advantage of the inherently more efficient behavioral design capabilities of C instead of manually coding structural requirements in HDL. Experienced hardware designers can also use the C2Verilog compiler to interface C models with existing hierarchical designs and incorporate optimized logic and memory macros for FPGA and ASIC hardware.
The C2Verilog compiler performs code optimization to create RTL Verilog that synthesizes more efficiently in hardware compared to previous attempts with line-by-line syntax translation. The user can also specify directives to the compiler using an extensive set of options selected on the command line or graphical user interface.
C2Verilog complements existing logic synthesis and simulation modeling products. The generated RTL Verilog code is compatible with industry standard logic synthesis products from Synopsys, Exemplar, and Synplicity, as well as Verilog simulators from Cadence, Model Technologies, and others.
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