San Jose, Calif.--Jan. 27, 1998--Express Logic announced ThreadXsupport for Argonaut RISC Cores' (ARC) high-performance 32-bitRISC microprocessor architecture. Express Logic's ThreadX provides real-time embedded ARC developers with the most technically advanced multitasking solution on the market today. Its pico-kernel design results in very high performance with extremely small memory requirements. ThreadX also provides ARC developers with significant technical innovations,including extremely fast software timers and a mechanism to help reducecontext switching called preemption-threshold.
The ARC 32-bit RISC processor core is ideal for today's cost-sensitive,high-performance applications. Demanding applications in wireless,telecommunications, and data storage should find the ARC solutionvery beneficial. ThreadX was designed for exactly the sameperformance-oriented applications. As a result, an increasing number of developers are turning to the ThreadX and ARC solution.
ARC is a very small, very fast 32-bit RISC microprocessor that isavailable in RTL source code. ARC is completely memory and processindependent. The ASRP architecture is a complete environment that offers the industry's first customizable processor, allowing the engineer to modify the instruction set for a specific application. It includes the ARC microprocessor, ASRP interfaces, Metaware Toolchain, ThreadX RTOS, and an easy-to-use Graphical Auto Installer.
The ARC microprocessor is designed for optimal silicon size, speed, and memory usage. Due to ARC's high performance and the ability to use only those instructions required for each application, an engineer can create a much smaller die size. This means ASRP-based designs are 30 to 50percent smaller than competing solutions. In a typical 0.35-(m process,ARC can run at speeds of 100 MHz, 115 MIPS, and is only 1.5-mm2 die size.
The ASRP architecture also supports the ability to add custom instructions,which allows the software engineer to fine tune the performance-criticalportion of the software. Software engineers state that only 10 to 20 percentof their software is performance-critical code, and with the ASRP architecture,they can add custom instructions that will eliminate or reduce bottlenecks,thereby dramatically improving the software performance.
In order to test and debug the custom instructions, Argonaut has created a hardware prototyping system that allow engineers to perform what-ifanalysis of core changes and debug software in real time.
The hardware prototyping system uses Altera's 100,000-gate Flex 10K100programmable logic device. A single Flex 10K100 device houses the ARC microprocessor core, extensions, memory cache, arbitrator and sequencer for external memory, and a personal computer interface. The engineer can make modifications to the ARC core and in real time implement those changes directly in the Flex device. That allows engineers to evaluate design trade-offs in performance and silicon area and begin writing software prior to committing to custom silicon. By using the ASRP prototyping system, it is possible to add new instructions in the morning and be creating and debugging software in the afternoon.
Argonaut RISC Cores
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