Santa Clara, Calif.--March 23, 1998--Chip Express Corp. announced the CX3000, 0.35-m CMOS technology for fast-turn, high-performance, and high-density gate array families. The CX3000 technology supports gate array production of up to 1.5 million logic gates plus up to 416k bits of embedded memory.
Using three- or four-layer metal interconnect structure, the CX3000 technology features high density (12,000-13,000 gates per mm2 ), about 20 percent greater density than most comparable standard cell solutions. The capability to increase the density is extremely important for high-volume production so that a required gate count can be implemented on a smaller device. The silicon for both CX3000 technology families is provided by Chartered Semiconductor Manufacturing (Singapore).
The CX3000 technology families offer low power consumption of 0.1 W/MHz/gate power consumption. Moreover, SRAM speeds of 290 MHz at 3.3 V were accomplished, with as quick as one day turnaround time available for prototypes, a couple of weeks for low-volume, and two month lead-time for high-volume production. Furthermore, the CX3000 technology features 3.3-V, 5-V, or mixed-voltage I/Os, and 5-V I/O tolerance at 3.3-V core. A unique feature enables powering the device with a single 5-V supply.
Currently, the CX3000 technology comprises of two families: the CX3001 for prototyping and low-volume production and the CX3002 for high-volume production. The density for these families ranges from 14k to 1.5 million logic gates plus 8k to 416k bits of embedded configurable SRAM or ROM. Platform capability ranges from 100 up to 608 I/O pads. A dual-oxide process was developed to provide 5-V I/O tolerance and mixed 3.3 V and 5 V with 0.35-m geometry. A variety of other I/O features are available, including 3.3-V PCI compliance at 66 MHz, GTL and USB support. In addition, the CX3001 and CX3002 family members include up to 4 embedded APLLs.
The CX3001 LPGA (laser programmable gate array) fast-turn prototypes are available in one-day delivery using Chip Express's QuICk laser micro-machining system that employs a disconnect methodology to remove all unneeded metal interconnect links from a generic, fully connected device, leaving only the desired ASIC interconnect pattern. For a low volume of CX3001 devices, the proprietary Onemask process technology is used in-house, to provide lead-time as short as a couple of weeks. Higher volumes, typically required for pilot production, are also available at further reduced cost in one-month lead-time with the Twomask process technology. The CX3002 devices, designed for cost-competitive high- volume production, are offered in only two-month lead-time using Hardarray process technology .
The CX3000 technology families support full-scan ATPG, without any speed or density penalties, using an extension of the previously proven test support package for the CX2000, 0.6-m technology. A wide range of popular packaging types are available for the CX3000 technology families, including PQFP, up to 240 pins; PGA, up to 391 pins; and BGA, up to 553 pins.
The laser system has already proven the capability to customize 0.35-m devices, generating working silicon. The Onemask process has yielded similar results.Some previously established customer designs are now converted to the CX3000 technology families. New designs with the 0.35-m technology process will begin within the next three weeks, and full production volume is expected to start in late Q2 / early Q3 of 1998.
A CX3001 family member with 500K logic gates plus 416k bits of memory in a typical package is priced at $127 per unit for a 3,000 device order. Lead-time is 4 weeks.A CX3002 family member with 350k logic gates plus 96k bits memory is priced at $15 per unit for a 100,000 device order. Lead-time is 8-12 weeks.
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